ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsRead/write acknowledge signalsTable A-18 shows the read/write acknowledge signals for the AXI master interface.Table A-18 Read/write acknowledge signalsSignal Type DescriptionRACKM Output Read acknowledgeWACKM Output Write acknowledgeA.9.2ACP signalsThe following sections describe the ACP signals:• Clock and configuration signals.• Write address channel signals.• Write data channel signals on page A-18.• Write response channel signals on page A-18.• Read address channel signals on page A-19.• Read data channel signals on page A-19.Clock and configuration signalsTable A-19 shows the clock and configuration signals for the ACP.Signal Type DescriptionTable A-19 Clock and configuration signalsA64n128S Input Selects 64-bit or 128-bit AXI slave bus width:0 128-bit bus width.1 64-bit bus width.ACLKENS Input AXI slave bus clock enable.AINACTS Input AXI slave inactive and no longer accepting requests.Write address channel signalsTable A-20 shows the write address channel signals for the ACP.Table A-20 Write address channel signalsSignal Type DescriptionAWADDRS[39:0] Input AddressAWBURSTS[1:0] Input Burst typeAWIDS[2:0] Input Request IDAWCACHES[3:0] Input Cache typeAWLENS[3:0] Input Burst lengthAWPROTS[2:0] Input Protection typeAWREADYS Output Address readyARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-17ID062913Non-Confidential