ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugTable 10-10 DBGWCR bit assignments (continued)Bits Name Function[12:5] BAS Byte Address Select. The processor implements an 8-bit Byte address select field,DBGWCR[12:5].A DBGWVR is programmed with a word-aligned address. This field enables the watchpoint to hitonly if certain bytes of the addressed word are accessed. The watchpoint hits if an access hits anybyte being watched, even if:• The access size is larger than the size of the region being watched.• The access is unaligned, and the base address of the access is not in the same word ofmemory as the address in the DBGWVR.• The access size is smaller than the size of region being watched.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[4:3] LSC Load/store access control. This field enables watchpoint matching on the type of access beingmade:b00 Reserved.b01 Match on any load, Load-Exclusive, or swap.b10 Match on any store, Store-Exclusive or swap.b11 Match on all type of access.[2:1] PAC Privileged Access Control. This field enables watchpoint matching conditional on the mode of theprocessor. This field is used with the SSC and PAC fields.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for possible valuesof the fields, and the access modes and security states that can be tested.[0] E Watchpoint enable. This bit enables the watchpoint:0 Watchpoint disabled.1 Watchpoint enabled.A watchpoint never generates a Watchpoint debug event when it is disabled.For more information about possible watchpoint values, see Watchpoint Value Registers onpage 10-17.10.4.9 Debug ROM Address RegisterThe DBGDRAR characteristics are:PurposeDefines the base physical address of a memory-mapped debugcomponent, usually a ROM Table that locates and describes thememory-mapped debug components in the system.Usage constraints This register is only visible in the CP14 interface, and therefore does nothave a memory offset.ConfigurationsThe DBGDRAR is:• a 64-bit register when accessed by the MRRC instruction• a 32-bit register when accessed by the MRC instruction.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-10 on page 10-21 shows the DBGDRAR bit assignments as a 32-bit register.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-20ID062913Non-Confidential