ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlWhen an instruction is trapped, the COND field is 0xE.4.3.47 Physical Address RegisterThe processor does not use any implementation-defined bits in the 32-bit format or 64-bitformat PAR, so these bits are UNK/SBZP.4.3.48 L2 Control RegisterThe L2CTLR characteristics are:PurposeProvides control options for the L2 memory system and ECC/paritysupport.Usage constraints The L2CTLR is:• A read/write register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher, with access rights that dependon the mode:— Read/write in Secure PL1 modes with some bits that areread-only.— Read-only and write-ignored in Non-secure PL1 and PL2modes.• This register can only be written when the L2 memory system isidle. ARM recommends that you write to this register after apowerup reset before the MMU is enabled and before any ACE orACP traffic has begun.If the register must be modified after a powerup reset sequence, toidle the L2 memory system, you must take the following steps:1. Disable the MMU from each processor followed by an ISB toensure the MMU disable operation is complete, then followedby a DSB to drain previous memory transactions.2. Ensure that the system has no outstanding AC channelcoherence requests to the Cortex-A15 MPCore processor.3. Ensure that the system has no outstanding ACP requests to theCortex-A15 MPCore processor.When the L2 is idle, the processor can update the L2CTLR followed by anISB. After the L2CTLR is updated, the MMUs can be enabled and normalACE and ACP traffic can resume.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-10 on page 4-10.Figure 4-38 on page 4-86 shows the L2CTLR bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-85ID062913Non-Confidential