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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Performance Monitor UnitTable 11-1 PMU register summary (continued)RegisternumberOffset CRn Op1 CRm Op2 Name Type Description1004 0xFB0 - - - - PMLAR WO Lock Access Register, see the <strong>ARM</strong> ®Architecture <strong>Reference</strong> <strong>Manual</strong><strong>ARM</strong>v7-A and <strong>ARM</strong>v7-R edition1005 0xFB4 - - - - PMLSR RO Lock Status Register, see the <strong>ARM</strong> ®Architecture <strong>Reference</strong> <strong>Manual</strong><strong>ARM</strong>v7-A and <strong>ARM</strong>v7-R edition1006 0xFB8 PMAUTHSTATUS RO Authentication Status Register, seethe <strong>ARM</strong> ® Architecture <strong>Reference</strong><strong>Manual</strong> <strong>ARM</strong>v7-A and <strong>ARM</strong>v7-Redition1007-1010 0xFBC-0xFC8 - - - - - - Reserved1011 0xFCC - - - - PMDEVTYPE RO Device Type Register, see the <strong>ARM</strong> ®Architecture <strong>Reference</strong> <strong>Manual</strong><strong>ARM</strong>v7-A and <strong>ARM</strong>v7-R edition1012 0xFD0 - - - - PMPID4 RO Peripheral Identification Registerson page 11-121013 0xFD4 - - - - PMPID5 RO1014 0xFD8 - - - - PMPID6 RO1015 0xFDC - - - - PMPID7 RO1016 0xFE0 - - - - PMPID0 RO1017 0xFE4 - - - - PMPID1 RO1018 0xFE8 - - - - PMPID2 RO1019 0xFEC - - - - PMPID3 RO1020 0xFF0 - - - - PMCID0 RO Component Identification Registerson page 11-131021 0xFF4 - - - - PMCID1 RO1022 0xFF8 - - - - PMCID2 RO1023 0xFFC - - - - PMCID3 RO- - c9 0 c12 5 PMSELR RW Event Counter Selection Register,see the <strong>ARM</strong> ® Architecture<strong>Reference</strong> <strong>Manual</strong> <strong>ARM</strong>v7-A and<strong>ARM</strong>v7-R edition<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 11-6ID062913Non-Confidential

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