ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.6 Intermediate table walk cachesThe Cortex-A15 MPCore processor implements dedicated caches that store intermediate levelsof translation table entries as part of a table walk. Cached entries are associated with an ASID.The TLB and the intermediate caches must be invalidated using the standard architectural rulethat states, if you change a translation table entry at any level of the walk that is associated witha particular ASID, you must invalidate entries that correspond to that ASID and its associatedVA range.Care is required when using the reserved ASID method for context switch. See the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.Example 5-1 shows how to synchronize ASID and TTBR changes using a reserved ASID.Example 5-1 Using a reserved ASID to synchronize ASID and TTBR changesIn this example, the operating system uses a particular reserved ASID value for thesynchronization of the ASID and the Translation Table Base Register. You can use this approachonly when the size of the mapping for any given virtual address is the same in the old and newtranslation tables. The example uses the value of 0.The software uses the following sequences that must be executed from memory marked asglobal:Change ASID to 0ISBChange Translation Table Base RegisterISBChange ASID to new valueISBIf the code relies on only leaf translation table entries that are cached, it can incorrectly assumethat entries tagged with the reserved ASID are not required to be flushed. For example:• Global leaf entries that remain valid or must be flushed for all ASIDs when modified.• Non-global leaf entries that are not used because the reserved ASID is not set outside thecontext switch code.The incorrect assumption leads to the following failure:• The context switch code sets the ASID to the reserved value.• Speculative fetching reads and caches the first level page table entry, using the currentTTBR, and tagging the entry with the reserved ASID. This is a pointer to a second leveltable.• Context switch completes.• Processing continues, and the process with the page tables terminates. The OS frees andreallocates the page table memory.• A later context switch sets the ASID to the reserved value• Speculative fetching makes use of the cached first level page table entry, because it istagged with the reserved ASID, and uses it to fetch a second level page table entry.Because the memory is reallocated and reused, the entry contains random data that canappear to be a valid, global entry. This second level page table entry is cached.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-8ID062913Non-Confidential