ARM Cortex-A15 MPCore Processor Technical Reference Manual

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DebugTable 10-16 DBGDSAR bit assignments (continued)Bits Name Function[31:12] SELFOFFSET[31:12] Bits[31:12] of the two’s complement offset from the base address defined by DBGDRAR to thephysical address where the debug registers are mapped. Bits[11:0] of the address are zero. SeeDebug ROM Address Register on page 10-20.If DBGDSAR.Valid is zero, the value of this field is UNKNOWN.[11:2] - Reserved.[1:0] Valid Valid bit. This field indicates whether the debug self address offset is valid:b00Offset is not valid.b11Offset is valid.10.4.15 Integration Output Control RegisterThe DBGITOCTRL characteristics are:PurposeControls signal outputs when bit[0] of the DBGITCTRL is set. SeeIntegration Mode Control Register on page 10-28.Usage constraints DBGITOCTRL is not accessible on the CP14 interface.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-18 shows the DBGITOCTRL bit assignments.31 4 3 2 1 0ReservednPMUIRQCTI PMUIRQCTI DBGRESTARTEDCTI DBGTRIGGERTable 10-17 shows the DBGITOCTRL bit assignments.Figure 10-18 DBGITOCTRL bit assignmentsTable 10-17 DBGITOCTRL bit assignmentsBits Name Function[31:4] - Reserved, SBZP.[3] nPMUIRQ This bit drives the nPMUIRQ output. When this bit is set to 1, the corresponding nPMUIRQsignal is cleared to 0. The reset value is 0.[2] CTI PMUIRQ This bit drives the internal signal equivalent to PMUIRQ that goes from the PerformanceMonitor Unit (PMU) to the Cross Trigger Interface (CTI). The reset value is 0.[1] CTI DBGRESTARTED This bit drives the internal signal that goes from the Debug unit to the CTI to acknowledgesuccess of a debug restart command. The reset value is 0.[0] CTI DBGTRIGGER This bit drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unitto the CTI. The reset value is 0.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-27ID062913Non-Confidential
Debug10.4.16 Integration Input Status RegisterThe DBGITISR characteristics are:PurposeEnables the values of signal inputs to be read when bit[0] of theDBGITCTRL is set. See Integration Mode Control Register.Usage constraints DBGITISR is not accessible on the extended CP14 interface.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-19 shows the DBGITISR bit assignments.31 3 2 1 0ReservedDBGSWENABLECTI DBGRESTARTCTI EDBGRQEDBGRQBits Name Function[31:4] - Reserved, RAZ.Table 10-18 shows the DBGITISR bit assignments.[3] DBGSWENABLE This field reads the state of the DBGSWENABLE input.Figure 10-19 DBGITISR bit assignmentsTable 10-18 DBGITISR bit assignments[2] CTI DBGRESTART CTI debug restart bit. This field reads the state of the debug restart input coming from the CTI intothe debug unit.[1] CTI EDBGRQ CTI debug request bit. This field reads the state of the debug request input coming from the CTIinto the debug unit.[0] EDBGRQ This field reads the state of the EDBGRQ input.10.4.17 Integration Mode Control RegisterThe DBGITCTRL characteristics are:PurposeSwitches the processor from its default functional mode into integrationmode, where test software can control directly the inputs and outputs ofthe processor, for integration testing or topology detection. When theprocessor is in integration mode, the test software uses the integrationregisters to drive output values and to read inputs.Usage constraints DBGITCTRL is not accessible on the extended CP14 interface.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-20 on page 10-29 shows the DBGITCTRL bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-28ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
Page 230 and 231: Generic Interrupt Controller8.2 GIC
Page 232 and 233: Generic Interrupt Controller8.2.4 I
Page 234 and 235: Generic Interrupt Controller8.3 GIC
Page 236 and 237: Generic Interrupt ControllerOffset
Page 238 and 239: Generic Interrupt ControllerTable 8
Page 240 and 241: Generic Interrupt ControllerPrivate
Page 242 and 243: Generic Interrupt Controller0x1D043
Page 244 and 245: Generic Interrupt ControllerThe Cor
Page 246 and 247: Generic Interrupt ControllerTable 8
Page 248 and 249: Generic Interrupt Controller8.3.8 V
Page 250 and 251: Generic Timer9.1 About the Generic
Page 252 and 253: Generic Timer9.3 Generic Timer prog
Page 254 and 255: Chapter 10DebugThis chapter describ
Page 256 and 257: Debug• Operating systems.• Hard
Page 258 and 259: DebugnPRESETDBGThis signal initiali
Page 260 and 261: DebugTable 10-1 CP14 debug register
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Page 264 and 265: DebugTable 10-2 DBGDIDR bit assignm
Page 266 and 267: DebugTable 10-4 shows the DBGDRCR b
Page 268 and 269: DebugConfigurationsAttributesThe pr
Page 270 and 271: DebugTable 10-8 DBGBCR bit assignme
Page 272 and 273: DebugTable 10-10 shows the DBGWCR b
Page 274 and 275: Debug31 12 11 2 1 0ROMADDR[31:12]Re
Page 276 and 277: Debug10.4.12 OS Lock Status Registe
Page 278 and 279: DebugTable 10-15 shows the DBGPRCR
Page 282 and 283: Debug31 1 0ReservedIntegration mode
Page 284 and 285: DebugTable 10-22 shows the DBGDEVID
Page 286 and 287: Debug10.4.23 Component Identificati
Page 288 and 289: Debug10.6 External debug interfaceT
Page 290 and 291: DebugIf software running on the pro
Page 292 and 293: Performance Monitor Unit11.1 About
Page 294 and 295: Performance Monitor Unit11.3 PMU re
Page 296 and 297: Performance Monitor UnitTable 11-1
Page 304 and 305: Performance Monitor Unit11.5 Effect
Page 308 and 309: Performance Monitor Unit11.7 Interr
Page 310 and 311: Chapter 12Program Trace MacrocellTh
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Page 314 and 315: Program Trace MacrocellYou can also
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Page 318 and 319: Program Trace Macrocellarchitecture
Page 320 and 321: Program Trace Macrocell12.6 Registe
Page 322 and 323: Program Trace MacrocellTable 12-4 P
Page 324 and 325: Program Trace MacrocellTable 12-5 E
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Page 328 and 329: Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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