ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionSoft resetThe full soft reset initializes all logic in each of the individual processor apart from the Debugand PTM logic in the CLK domain. All breakpoints and watchpoints are retained during a softreset sequence. By asserting only nCORERESET, the reset domains controlled bynDBGRESET, nPRESETDBG, and nL2RESET, that is, the Debug and PTM in CLK, DebugAPB in PCLKDBG, and the shared L2 memory system, GIC, and Generic Timer domains, arenot reset.Figure 2-8 shows the full soft reset sequence for the Cortex-A15 MPCore processor.CLKnCPUPORESET[3:0]nDBGRESET[3:0]nL2RESETnPRESETDBGHIGH-inactiveHIGH-inactiveHIGH-inactiveHIGH-inactivenCORERESET[3:0]16 CLK cycles minimumnCXRESET[3:0]optional16 CLK cycles minimumFigure 2-8 Soft reset timingOn full soft reset for the Cortex-A15 MPCore processor, perform the following reset sequence:1. You must apply steps 1 to 8 in the processor powerdown sequence, see Processor powerdomain on page 2-30, and wait until STANDBYWFI is asserted, indicating that theprocessor is idle, before asserting nCORERESET for that processor.2. Apply nCORERESET, nCXRESET can be asserted, but is not required.3. After both resets have been asserted for 5 cycles, the clamps can be released.4. nCORERESET must be asserted for at least 16 CLK cycles.5. If nCXRESET is asserted, both resets must be deasserted in the same cycle.Individual processor soft reset initializes all logic in a single processor apart from its Debug,PTM, breakpoint and watchpoint logic. Breakpoints and watchpoints for that processor areretained. You must apply the correct sequence before applying soft reset to that processor.For individual processor soft reset:• You must apply steps 1 to 8 in the processor powerdown sequence, see Processor powerdomain on page 2-30, and wait until STANDBYWFI is asserted, indicating that theprocessor is idle, before asserting nCORERESET for that processor.NoteFor a single processor configuration you can omit step 3 that clears the ACTLR SMP bit.• nCORERESET for that processor must be asserted for at least 16 CLK cycles.• nL2RESET must not be asserted while any individual processor is active.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-17ID062913Non-Confidential