ARM Cortex-A15 MPCore Processor Technical Reference Manual

Performance Monitor UnitPMCEID1[31:0] is reserved.Table 11-4 Common Event Identification Register 0 bit assignmentsBit Event number Event implemented if set to 1 or not implemented if set to 0[31] 0x1F Reserved.[30] 0x1E[29] 0x1D Bus cycle. This event is implemented.[28] 0x1C Instruction architecturally executed, condition check pass, write to translation table base. This event isimplemented.[27] 0x1B Instruction speculatively executed. This event is implemented.[26] 0x1A Local memory error. This event is implemented.[25] 0x19 Bus access. This event is implemented.[24] 0x18 Level 2 data cache write-back. This event is implemented.[23] 0x17 Level 2 data cache refill. This event is implemented.[22] 0x16 Level 2 data cache access. This event is implemented.[21] 0x15 Level 1 data cache write-back. This event is implemented.[20] 0x14 Level 1 instruction cache access. This event is implemented.[19] 0x13 Data memory access. This event is implemented.[18] 0x12 Predictable branch speculatively executed. This bit is RAO.[17] 0x11 Cycle, this bit is RAO.[16] 0x10 Mispredicted or not predicted branch speculatively executed. This bit is RAO.[15] 0x0F Instruction architecturally executed, condition check pass, unaligned load or store. This event is notimplemented.[14] 0x0E Instruction architecturally executed, condition check pass, procedure return. This event is notimplemented.[13] 0x0D Instruction architecturally executed, immediate branch. This event is not implemented.[12] 0x0C Instruction architecturally executed, condition check pass, software change of the PC. This event is notimplemented.[11] 0x0B Instruction architecturally executed, condition check pass, write to CONTEXTIDR. This event isimplemented.[10] 0x0A Instruction architecturally executed, condition check pass, exception return. This event is implemented.[9] 0x09 Exception taken. This event is implemented.[8] 0x08 Instruction architecturally executed, this bit is RAO.[7] 0x07 Instruction architecturally executed, condition check pass, store. This event is not implemented.[6] 0x06 Instruction architecturally executed, condition check pass, load. This event is not implemented.[5] 0x05 Level 1 data TLB refill. This event is implemented.[4] 0x04 Level 1 data cache access. This bit is RAO.[3] 0x03 Level 1 data cache refill. This bit is RAO.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-11ID062913Non-Confidential