ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-8 Differences between issue G and issue H (continued)Change Location AffectsCorrected description for bits[3:0] PCSROffset of the DebugDevice ID Register 1Added a footnote to the PMU events table to indicate thatevent count is encoded as plain binary number to accomodatecount values of more than one.Updated the configurations information for all theAdvanced SIMD and VFP system registersDebug Device ID Register 1 on page 10-30Table 11-7 on page 11-15Chapter 14 NEON and VFP UnitAll revisionsAll revisionsAll revisionsTable B-9 Differences between issue H and issue IChange Location AffectsUpdated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r4p0Updated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r4p0Added bit[25] to the L2 Auxiliary Control Register L2 Auxiliary Control Register on page 4-100 r4p0Added a new L2 memory interface attribute for snoopacceptance capabilityTable 7-4 on page 7-12r4p0Added a new table for the ACP L2 memory interface attribute Table 7-7 on page 7-18 r4p0Moved the step for asserting ACINACTM to after the step forcleaning and invalidating all data from the L2 data cacheAdded a step for setting the DBGOSDLR.DLK to force thedebug interfaces to be quiescentProcessor powerdown mode on page 2-36Dormant mode on page 2-35r4p0r4p0Added L1 data TLB support for 1MB page table entries • Table 1-1 on page 1-7• L1 data TLB on page 5-3r4p0Added a sentence to indicate that the GIC does not support a1:1 clock frequency ratio• Clocks on page 2-8• GIC clock frequency on page 8-3All revisionsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-7ID062913Non-Confidential