ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionIf the individual processor cannot safely enter quiescent state when QREQn is asserted LOW,the Cortex-A15 MPCore processor asserts QDENY HIGH instead of asserting QACCEPTnLOW. When this occurs, the external power controller cannot lower the voltage of thatprocessor. The external power controller must then deassert QREQn HIGH, after which theprocessor deasserts QDENY LOW.If the clocks for a quiescent processor must be restarted, for example, to handle a snoop or toexit the WFI or WFE low-power state, the QACTIVE signal asserts HIGH. This indicates tothe external power controller that it must allow that processor to exit quiescent state. To do this,the external power controller must first restore that processor power domain to a stable runningvoltage. The external power controller then deasserts QREQn. When this signal is deasserted,the Cortex-A15 MPCore processor can restart the clocks to that individual processor and thendeasserts QACCEPTn.Figure 2-14 shows a typical sequence where the external power controller places the processorin retention state. The processor executes a WFI instruction. STANDBYWFI is asserted andQACTIVE is deasserted. The external power controller asserts QREQn LOW to indicate thatit wants to put that processor into retention. While the processor is still in WFI low-power stateand the clocks are stopped, QACCEPTn is asserted LOW. At this point, the processor is inquiescent state and the external power controller can lower the voltage. During retention, asnoop must access the cache of the quiescent processor. The QACTIVE signal is assertedHIGH to request an exit from retention. The external power controller raises the voltage of thatprocessor to running levels and deasserts QREQn. The clocks are started and the snoop canproceed. QACCEPTn is then deasserted HIGH. After the snoop is complete, QACTIVE isdeasserted LOW. QREQn and QACCEPTn are then asserted LOW. The processor hasre-entered quiescent state and the external power controller can lower the voltage once again.When the processor is ready to exit WFI low-power state, QACTIVE is asserted HIGH.QREQn is then deasserted HIGH, the processor exits WFI low-power state, and QACCEPTnis deasserted HIGH.CLKQACTIVEQREQnQACCEPTnQDENYSTANDBYWFIretentionretentionFigure 2-14 WFI successful retention timingFigure 2-15 on page 2-26 shows a sequence where the external power controller attempts to butfails to take a processor to retention voltage levels. The processor enters WFI low-power stateand deasserts QACTIVE. The external power controller asserts QREQn LOW and QDENY isasserted HIGH, followed by the deassertions of QREQn and QDENY. This sequence is thenrepeated.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-25ID062913Non-Confidential