ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTo access the CTR, read the CP15 register with:MRC p15, 0, , c0, c0, 1; Read Cache Type Register4.3.3 TCM Type RegisterThe processor does not implement instruction or data Tightly Coupled Memory (TCM), so thisregister is always RAZ/WI.4.3.4 TLB Type RegisterThe TLBTR characteristics are:PurposeProvides information about the TLB implementation.Usage constraints The TLBTR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-3 shows the TLBTR bit assignments.31 1 0ReservednUTable 4-31 shows the TLBTR bit assignments.Figure 4-3 TLBTR bit assignmentsTable 4-31 TLBTR bit assignmentsBits Name Function[31:1] - Reserved, RAZ.[0] nU Not Unified. Indicates whether the implementation has a unified TLB:0x0Processor has a unified TLB.To access the TLBTR, read the CP15 register with:MRC p15, 0, , c0, c0, 3; Read TLB Type Register4.3.5 Multiprocessor Affinity RegisterThe MPIDR characteristics are:PurposeProvides an additional processor identification mechanism for schedulingpurposes in a multiprocessor system.Usage constraints The MPIDR is:• A read-only register.• Common to the Secure and Non-secure states.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-29ID062913Non-Confidential