ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace Macrocell12.5 PTM programmers modelThe programmers model enables you to use the PTM registers to control the macrocell. Thissection describes the mechanisms for programming the registers used to set up the trace andtriggering facilities of the macrocell in:• Modes of operation.• Register short names on page 12-8.• Event definitions on page 12-9.• Turning off the PTM on page 12-9.• Interaction with the performance monitoring unit on page 12-10.12.5.1 Modes of operationWhen the PTM is powered up or reset, you must program all PTM registers before you enabletracing. If you do not do so, the trace results are UNPREDICTABLE.When programming the PTM registers you must enable all the changes at the same time. Forexample, if the counter is reprogrammed before the trigger condition has been correctly set up,it might start to count based on incorrect events.You access the PTM registers through the CoreSight Debug APB bus. The PTM implements theCoreSight lock access mechanism, and can distinguish between memory-mapped accesses fromon-chip software and memory-mapped accesses from a debugger, for example by using theCoreSight Debug Access Port (DAP).See the CoreSight Program Flow Trace Architecture Specification for more information aboutprogramming the PTM.The following sections describe how you control PTM programming:• Using the Programming bit.• Programming registers on page 12-8.Using the Programming bitUse the Programming bit in the Main Control Register, see Main Control Register onpage 12-14, to disable all operations during programming.When the Programming bit is set to 0 you must not write to registers other than the Main ControlRegister, because this can lead to UNPREDICTABLE behavior.When setting the Programming bit, you must not change any other bits of the Main ControlRegister. You must only change the value of bits other than the Programming bit of the ControlRegister when bit[1] of the Status Register is set to 1. ARM recommends that you use aread-modify-write procedure when changing the Main Control Register. For information on theStatus Register, see the CoreSight Program Flow Trace Architecture Specification.When the Programming bit is set to 1:• The FIFO is permitted to empty and no more trace is produced.• The counters, sequencer, and start/stop block are held in their current state.• The external outputs are forced LOW.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-7ID062913Non-Confidential