ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-20 Cache and branch predictor maintenance operations (continued)Name CRn Op1 CRm Op2 Reset DescriptionDCCMVAU c11 1 UNK Data cache clean by MVA to PoU, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionDCCIMVAC c14 1 UNK Data cache clean and invalidate by MVA to PoC, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionDCCISW 2 UNK Data cache clean and invalidate by set/way, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editiona. PoU = Point of Unification. If BROADCASTINNER is LOW, the PoU is in the L1 data cache. If BROADCASTINNER is HIGH, thePoU is outside of the processor and is dependent on the external memory system.b. PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.4.2.21 TLB maintenance operationsTable 4-21 shows the 32-bit wide TLB maintenance operations.Table 4-21 TLB maintenance operationsName CRn Op1 CRm Op2 Reset DescriptionTLBIALLIS c8 0 c3 0 UNK Invalidate entire unified TLB Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionTLBIMVAIS 1 UNK Invalidate unified TLB by MVA and ASID Inner Shareable, seethe ARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionTLBIASIDIS 2 UNK Invalidate unified TLB by ASID Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionTLBIMVAAIS 3 UNK Invalidate unified TLB by MVA all ASID Inner Shareable, seethe ARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionITLBIALL c5 0 UNK Invalidate entire instruction TLB, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionITLBIMVA 1 UNK Invalidate instruction TLB entry by MVA and ASID, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-ReditionITLBIASID 2 UNK Invalidate instruction TLB by ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionDTLBIALL c6 0 UNK Invalidate entire data TLB, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionDTLBIMVA 1 UNK Invalidate data TLB entry by MVA and ASID, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionDTLBIASID 2 UNK Invalidate data TLB by ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionTLBIALL c7 0 UNK Invalidate entire unified TLB, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-18ID062913Non-Confidential