ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory SystemNote• The L2 data RAM total latency is set to a maximum of 8 cycles.• Each data slice adds 2 cycles and affects the L2 data and data ECC RAMs.• Setting data setup to 1 adds 1 cycle.• Slice and setup have priority over programmed latency in determining the total adjustedRAM latency.Example 7-3 shows a data RAM access with 4 cycles total RAM latency.Example 7-3 Data RAM access with 4 cycles total latencyWhen data slice = 0, L2CTLR[5] = 0, L2CTLR[2:0] = 3'b011, the following applies:• no slice cycle.• no setup cycle.• 4 cycles data RAM access.• 4 cycles total data RAM latency.Example 7-4 shows a data RAM access with 8 cycles total RAM latency.Example 7-4 Data RAM access with 8 cycles total latencyWhen data slice = 2, L2CTLR[5] = 1, L2CTLR[2:0] = 3'b011, the following applies:• 4 slice cycles.• 1 setup cycle.• 3 cycles data RAM access adjusted because of slice and setup values.• 8 cycles total data RAM latency.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-7ID062913Non-Confidential