ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-69 L2CTLR bit assignments (continued)Bits Name Function[11:10] Data RAM slice L2 data RAM slice:b000 slice.b011 slice.b102 slices.b11Invalid value.These are read-only bits and the reset value of this field is set to the number of data RAMslice present in the configuration. See Register slice support for large cache sizes onpage 7-5 for more information.[9] Tag RAM setup L2 tag RAM setup:0 0 cycle. This the reset value.1 1 cycle.[8:6] Tag RAM latency L2 tag RAM latency:b000 2 cycles. This is the reset value.b001 2 cycles.b010 3 cycles.b011 4 cycles.b1xx 5 cycles, where x can be any value.[5] Data RAM setup L2 data RAM setup:0 0 cycle. This the reset value.1 1 cycle.[4:3] - Reserved, RAZ/WI.[2:0] Data RAM latency L2 data RAM latency:b000 2 cycles. This is the reset value.b001 2 cycles.b010 3 cycles.b011 4 cycles.b100 5 cycles.b101 6 cycles.b110 7 cycles.b111 8 cycles.To access the L2CTLR, read or write the CP15 register with:MRC p15, 1, , c9, c0, 2; Read L2 Control RegisterMCR p15, 1, , c9, c0, 2; Write L2 Control Register4.3.49 L2 Extended Control RegisterThe L2ECTLR characteristics are:PurposeProvides additional control options for the L2 memory system.Usage constraints The L2ECTLR is:• A read/write register.• Common to the Secure and Non-secure states.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-87ID062913Non-Confidential