ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt Controller8.2.4 Interrupt priority levelsWhen a processor uses the GIC rather than the external nFIQ signal inlegacy mode, by enabling its own CPU interface, the nFIQ signal istreated like other interrupt lines and uses ID28. The interrupt isactive-LOW level-sensitive.Secure Physical Timer event (PPI1)This is the event generated from the Secure physical timer and usesID29. The interrupt is active-LOW level-sensitive.Non-secure Physical Timer event (PPI2)This is the event generated from the Non-secure physical timer anduses ID30. The interrupt is active-LOW level-sensitive.Legacy nIRQ signal (PPI3)In legacy IRQ mode, the external nIRQ signal bypasses the interruptdistributor logic and directly drives the interrupt request to thecorresponding processor.When a processor uses the GIC rather than the external nIRQ signal inlegacy mode, by enabling its own CPU interface, the nIRQ signal istreated like other interrupt lines and uses ID31. The interrupt isactive-LOW level-sensitive.Virtual Timer event (PPI4)This is the event generated from the virtual timer and uses ID27. Theinterrupt is active-LOW level-sensitive.Hypervisor Timer event (PPI5)This is the event generated from the physical timer in Hypervisor modeand uses ID26. The interrupt is active-LOW level-sensitive.Virtual Maintenance Interrupt (PPI6)The Virtualization Extensions support in the ARM Generic InterruptController Architecture Specification permits for a maintenanceinterrupt to be generated under several conditions. The virtualmaintenance interrupt uses ID25. The interrupt is active-HIGHlevel-sensitive.Shared Peripheral InterruptsSPIs are triggered by events generated on associated interrupt input lines. TheGIC can support up to 224 SPIs corresponding to the external IRQS[223:0]signal. The number of SPIs available depends on the implemented configurationof the Cortex-A15 MPCore processor. The permitted values are 0, 32, 64, 96, 128,160, 192, or 224. SPIs start at ID32. The SPIs can be configured to beedge-triggered or active-HIGH level-sensitive.The Cortex-A15 MPCore processor implements a 5-bit version of the interrupt priority field for32 interrupt priority levels in Secure state.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-5ID062913Non-Confidential