ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional Description• NEON and VFP unit on page 2-4.• Generic Interrupt Controller on page 2-4.• Generic Timer on page 2-4.• Debug and trace on page 2-4.Instruction fetchThe instruction fetch unit fetches instructions from the L1 instruction cache and delivers up tothree instructions per cycle to the instruction decode unit. It supports dynamic and static branchprediction. The instruction fetch unit includes:• L1 instruction cache that is a 32KB 2-way set-associative cache with 64 bytes cache lineand optional parity protection per 16-bits.• 2-level dynamic predictor with BTB for fast target generation.• Return stack.• Static branch predictor.• Indirect predictor.• 32-entry fully-associative L1 instruction TLB.Instruction decodeThe instruction decode unit decodes the following instructions:• ARM.• Thumb.• ThumbEE.• Advanced SIMD.• CP14.• CP15.The instruction decode unit also performs register renaming to facilitate out-of-order executionby removing Write-After-Write (WAW) and Write-After-Read (WAR) hazards. A loop bufferprovides additional power savings while executing small instruction loops.Instruction dispatchThe instruction dispatch unit controls when the decoded instructions can be dispatched to theexecution pipelines and when the returned results can be retired. It includes:• The ARM core general purpose registers.• The Advanced SIMD and VFP extension register set.• The CP14 and CP15 registers.• The APSR and FPSCR flag bits.Integer executeThe integer execute unit includes:• Two symmetric Arithmetic Logical Unit (ALU) pipelines.• Integer multiply-accumulate pipeline.• Iterative integer divide hardware.• Branch and instruction condition codes resolution logic.• Result forwarding and comparator logic.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-3ID062913Non-Confidential