ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-58 HDCR bit assignments (continued)Bits Name Function[6] TPM Trap Performance Monitors accesses:0 Has no effect on Performance Monitors accesses.1 Trap valid Non-secure Performance Monitors accesses to Hyp mode.When this bit is set to 1, any valid Non-secure access to the Performance Monitors registers istrapped to Hyp mode. This bit resets to 0. See the ARM ® Architecture Reference Manual ARMv7-Aand ARMv7-R edition for more information.[5] TPMCR Trap Performance Monitor Control Register accesses:0 Has no effect on PMCR accesses.1 Trap valid Non-secure PMCR accesses to Hyp mode.When this bit is set to 1, any valid Non-secure access to the PMCR is trapped to Hyp mode. Thisbit resets to 0. See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition formore information.[4:0] HPMN Defines the number of Performance Monitors counters that are accessible from Non-secure PL1modes, and from Non-secure PL0 modes if unprivileged access is enabled.In Non-secure state, HPMN divides the Performance Monitors counters as follows:If PMXEVCNTR is accessing Performance Monitors counter n then, in Non-secure state:• If n is in the range 0 ≤n