ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-9 c8 register summary (continued)Op1 CRm Op2 Name Reset Description2 TLBIASID UNK Invalidate unified TLB by ASID match, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition3 TLBIMVAA UNK Invalidate unified TLB entries by MVA all ASID, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition4 c3 0 TLBIALLHIS UNK Invalidate entire Hyp unified TLB Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition1 TLBIMVAHIS UNK Invalidate Hyp unified TLB entry by MVA Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition4 TLBIALLNSNHIS UNK Invalidate entire Non-secure non-Hyp unified TLB Inner Shareable, seethe ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R editionc7 0 TLBIALLH UNK Invalidate entire Hyp unified TLB, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition1 TLBIMVAH UNK Invalidate Hyp unified TLB entry by MVA, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition4 TLBIALLNSNH UNK Invalidate entire Non-secure non-Hyp unified TLB, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition4.2.9 c9 registersTable 4-10 shows the 32-bit wide CP15 system control registers when CRn is c9.Table 4-10 c9 register summaryOp1 CRm Op2 Name Reset Description0 c12 0 PMCR 0x410F3000 Performance Monitor Control Register on page 11-81 PMNCNTENSET UNK Performance Monitor Count Enable Set Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition2 PMNCNTENCLR UNK Performance Monitor Count Enable Clear Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition3 PMOVSR UNK Performance Monitor Overflow Flag Status Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition4 PMSWINC UNK Performance Monitor Software Increment Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition5 PMSELR UNK Performance Monitor Event Counter Selection Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition6 PMCEID0 0x3FFF0F3F Performance Monitor Common Event Identification Register 0 onpage 11-107 PMCEID1 0x00000000 Performance Monitor Common Event Identification Register 1 onpage 11-12c13 0 PMCCNTR UNK Performance Monitor Cycle Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-10ID062913Non-Confidential