ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-53 ACTLR bit assignments (continued)Bits Name Function[9] a Disable flag renaming optimization Disables flag renaming optimization:0 Enables normal flag renaming optimization. This is the resetvalue.1 Disables normal flag renaming optimization.[8] a Execute WFI instruction as a NOPinstruction[7] a Execute WFE instruction as a NOPinstructionExecutes WFI instruction as a NOP instruction:0 Executes WFI instruction as defined in the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition. This is thereset value.1 Executes WFI instruction as a NOP instruction, and does not putthe processor in low-power state.Executes WFE instruction as a NOP instruction:0 Executes WFE instruction as defined in the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition. This is thereset value.1 Executes WFE instruction as a NOP instruction, and does not putthe processor in low-power state.[6] SMP Enables the processor to receive instruction cache, BTB, and TLB maintenanceoperations from other processors. You must set this bit before enabling thecaches and MMU, or performing any cache and TLB maintenance operations.You must clear this bit to 0 during a processor powerdown sequence. See Powermanagement on page 2-21:0 Disables receiving of instruction cache, BTB, and TLBmaintenance operations. This is the reset value.1 Enables receiving of instruction cache, BTB, and TLBmaintenance operations.Note• Any processor instruction cache, BTB, and TLB maintenance operationscan execute the request, regardless of the value of the SMP bit.• This bit has no impact on data cache maintenance operations.• In the Cortex-A15 MPCore processor, the L1 data cache and L2 cache arealways coherent, for shared or non-shared data, regardless of the value ofthe SMP bit.[5] a Execute PLD instructions as a NOP Execute PLD and PLDW instructions as a NOP instruction:0 Executes PLD and PLDW instructions as defined in the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-Redition. This is the reset value.1 Executes PLD and PLDW instructions as a NOP instruction.[4] a Disable indirect predictor Disables indirect predictor:0 Enables indirect predictor. This is the reset value.1 Disables indirect predictor.[3] a Disable micro-BTB Disables micro-Branch Target Buffer (BTB):0 Enables micro-BTB. This is the reset value.1 Disables micro-BTB.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-61ID062913Non-Confidential