ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System ControlTable 4-8 c7 register summary (continued)Op1 CRm Op2 Name Reset Description6 BPIALL UNK Invalidate all branch predictors, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition7 BPIMVA UNK Invalidate MVA from branch predictors, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc6 1 DCIMVAC UNK Invalidate data cache line by MVA to PoC b , see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition2 DCISW UNK Invalidate data cache line by set/way, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc8 0 ATS1CPR UNK Stage 1 current state PL1 read, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 ATS1CPW UNK Stage 1 current state PL1 write, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition2 ATS1CUR UNK Stage 1 current state unprivileged read, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition3 ATS1CUW UNK Stage 1 current state unprivileged write, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition4 ATS12NSOPR UNK Stages 1 and 2 Non-secure PL1 read, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition5 ATS12NSOPW UNK Stages 1 and 2 Non-secure PL1 write, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition6 ATS12NSOUR UNK Stages 1 and 2 Non-secure unprivileged read, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition7 ATS12NSOUW UNK Stages 1 and 2 Non-secure unprivileged write, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionc10 1 DCCMVAC UNK Clean data cache line by MVA to PoC, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition2 DCCSW UNK Clean data cache line by set/way, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition4 CP15DSB UNK Data Synchronization Barrier operation, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R edition5 CP15DMB UNK Data Memory Barrier operation, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc11 1 DCCMVAU UNK Clean data cache line by MVA to PoU, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc13 1 NOP UNK No Operation, see the ARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionc14 1 DCCIMVAC UNK Clean and invalidate data cache line by MVA to PoC, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-8ID062913Non-Confidential
System ControlTable 4-8 c7 register summary (continued)Op1 CRm Op2 Name Reset Description2 DCCISW UNK Clean and invalidate data cache line by set/way, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition4 c8 0 ATS1HR UNK Stage 1 Hyp mode read, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 ATS1HW UNK Stage 1 Hyp mode write, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R editiona. PoU = Point of Unification. If BROADCASTINNER is LOW, the PoU is in the L1 data cache. If BROADCASTINNER is HIGH thenthe PoU is outside of the processor and is dependent on the external memory system.b. PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.4.2.8 c8 registersTable 4-9 shows the 32-bit wide CP15 system control registers when CRn is c8.Table 4-9 c8 register summaryOp1 CRm Op2 Name Reset Description0 c3 0 TLBIALLIS UNK Invalidate entire TLB Inner Shareable, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition1 TLBIMVAIS UNK Invalidate unified TLB entry by MVA and ASID Inner Shareable, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition2 TLBIASIDIS UNK Invalidate unified TLB by ASID match Inner Shareable, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition3 TLBIMVAAIS UNK Invalidate unified TLB entry by MVA all ASID Inner Shareable, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R editionc5 0 ITLBIALL UNK Invalidate instruction TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 ITLBIMVA UNK Invalidate instruction TLB entry by MVA and ASID, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R edition2 ITLBIASID UNK Invalidate instruction TLB by ASID match, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionc6 0 DTLBIALL UNK Invalidate data TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 DTLBIMVA UNK Invalidate data TLB entry by MVA and ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition2 DTLBIASID UNK Invalidate data TLB by ASID match, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionc7 0 TLBIALL UNK Invalidate unified TLB, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 TLBIMVA UNK Invalidate unified TLB by MVA and ASID, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-9ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
Page 31 and 32: Functional Description2.2 Interface
Page 33 and 34: Functional Description2.3 Clocking
Page 35 and 36: Functional DescriptionFigure 2-5 sh
Page 37: Functional DescriptionAll resets ar
Page 41 and 42: Functional DescriptionPowerup reset
Page 43 and 44: Functional Description• nPRESETDB
Page 45 and 46: Functional Description• L2 unifie
Page 47 and 48: Functional DescriptionOn entry into
Page 49 and 50: Functional DescriptionWhen the proc
Page 51 and 52: Functional DescriptionNoteFigure 2-
Page 53 and 54: Functional DescriptionRegional cloc
Page 55 and 56: Functional DescriptionTable 2-3 Val
Page 57 and 58: Functional Description4. Release th
Page 59 and 60: Functional DescriptionDebug power d
Page 61 and 62: Functional DescriptionNoteAfter a p
Page 63 and 64: Functional DescriptionThe external
Page 65 and 66: Programmers Model3.1 About the prog
Page 67 and 68: Programmers Model3.3 Advanced SIMD
Page 69 and 70: Programmers ModelYou can use the CP
Page 71 and 72: Programmers Model3.6 Large Physical
Page 73 and 74: Programmers Model3.8 Modes of opera
Page 75 and 76: Chapter 4System ControlThis chapter
Page 77 and 78: System Control4.2 Register summaryT
Page 79 and 80: System ControlOp1 CRm Op2 Name Rese
Page 81: System ControlTable 4-6 c5 register
Page 85 and 86: System ControlTable 4-10 c9 registe
Page 87 and 88: System Control4.2.14 c15 registersT
Page 89 and 90: System ControlName CRn Op1 CRm Op2
Page 91 and 92: System Control4.2.19 Other system c
Page 95 and 96: System Control4.2.24 Performance mo
Page 97 and 98: System Control4.2.26 Virtualization
Page 101 and 102: System Control4.3 Register descript
Page 103 and 104: System ControlTo access the CTR, re
Page 106 and 107: System ControlTable 4-34 shows the
Page 110 and 111: System Control4.3.12 Memory Model F
Page 114 and 115: System ControlTable 4-40 ID_MMFR3 b
Page 116 and 117: System Control31 28 27 24 23 20 19
Page 118 and 119: System ControlTable 4-43 ID_ISAR2 b
Page 126 and 127: System ControlConfigurationsAvailab
Page 128 and 129: System ControlMCR p15, 4, , c0, c0,
Page 130 and 131: System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlTable 4-58 shows the
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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