ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-79 L2MERRSR bit assignments (continued)Bits Name Function[31] Valid Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, itremains set until the register is written.The reset value is 0.[30:24] RAMID RAM Identifier. Indicates the RAM where the first memory error occurred:0x10 L2 tag RAM.0x11 L2 data RAM.0x12 L2 snoop tag RAM.0x14 L2 dirty RAM.[23:22] - Reserved, RAZ/WI.[21:18] CPUID/Way Indicates which processor and way of the RAM where the first memory error occurred.For L2 tag, data, and dirty RAMs, bits[21:18] indicate one of 16 ways, from way 0 to way 15.b0000 CPU0 tag, way 0.b0001 CPU0 tag, way 1.b0010 CPU1 tag, way 0.b0011 CPU1 tag, way 1.b0100 CPU2 tag, way 0.b0101 CPU2 tag, way 1.b0110 CPU3 tag, way 0.b0111 CPU3 tag, way 1.For L2 snoop tag RAM:• Bits[20:19] indicate which processor of the L1 tag RAM.• Bit[18] indicates which way of the tag RAM.[17:0] Index Indicates the index address of the first memory error.Note• If two or more memory errors in the same RAM occur in the same cycle, only one erroris reported.• If two or more first memory error events from different RAMs occur in the same cycle,one of the errors is selected arbitrarily, while the Other error count field is onlyincremented by one.• If two or more memory error events from different RAMs, that do not match the RAMID,bank, way, or index information in this register while the sticky Valid bit is set, occur inthe same cycle, the Other error count field is only incremented by one.To access the L2MERRSR, read or write the CP15 register with:MRRC p15, 1, , , c15; Read L2 Memory Error Syndrome RegisterMCCR p15, 1, , , c15; Write L2 Memory Error Syndrome RegisterARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-110ID062913Non-Confidential