ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System• WRAP N (N:1-8) 64-bit write transfers.• WRAP N (N:1-4) 128-bit write transfers.• INCR N (N:1-16) 8-bit read transfers.• INCR N (N:1-16) 16-bit read transfers.• INCR N (N:1-16) 32-bit read transfers.• INCR N (N:1-8) 64-bit read transfers.• INCR N (N:1-4) 128-bit read transfers.• INCR N (N:1-16) 8-bit write transfers.• INCR N (N:1-16) 16-bit write transfers.• INCR N (N:1-16) 32-bit write transfers.• INCR N (N:1-8) 64-bit write transfers.• INCR N (N:1-4) 128-bit write transfers.• FIXED N (N:1-16) 8-bit read transfers.• FIXED N (N:1-16) 16-bit read transfers.• FIXED N (N:1-16) 32-bit read transfers.• FIXED N (N:1-8) 64-bit read transfers.• FIXED N (N:1-4) 128-bit read transfers.• FIXED N (N:1-16) 8-bit write transfers.• FIXED N (N:1-16) 16-bit write transfers.• FIXED N (N:1-16) 32-bit write transfers.• FIXED N (N:1-8) 64-bit write transfers.• FIXED N (N:1-4) 128-bit write transfers.Note• ACP requests with burst mode INCR that crosses a 64-byte aligned boundary are brokeninto multiple ACE requests of burst type INCR and of size 64 bytes or less.• ACP requests with burst mode WRAP that crosses a 64-byte aligned boundary are brokeninto multiple ACE requests of burst type INCR of size 64 bytes or less. The received datais returned on the ACP port in the order required by the WRAP request.• ACP requests with burst mode FIXED that requests more than 64 bytes generate multipleFIXED requests on the ACE of size 64 bytes or less.7.7.4 Distributed virtual memory transactionsIn a system where the Cortex-A15 MPCore processor can receive a Distributed Virtual Memory(DVM) synchronization message over the AXI master snoop address channel, BRESP for anywrite transaction must not be asserted to the processor until all AXI masters that might haveinitiated the DVM synchronization request observe the transaction.NoteThe Cortex-A15 MPCore processor does not support a multi-part DVM hint message.7.7.5 Cache maintenance transactionsThe BROADCASTCACHEMAINT signal controls the broadcasting of cache maintenanceoperations on the AR-channel. For more information on cache maintenance operations, see theARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition and the ARM ® AMBA ®AXI and ACE Protocol Specification AXI3 , AXI4 , and AXI4-Lite , ACE and ACE-Lite .ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-14ID062913Non-Confidential