ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-58 shows the HDCR bit assignments.Table 4-58 HDCR bit assignmentsBits Name Function[31:12] - Reserved, UNK/SBZP.[11] TDRA Trap Debug ROM Access:0 Has no effect on Debug ROM accesses.1 Trap valid Non-secure Debug ROM accesses to Hyp mode.When this bit is set to 1, any valid Non-secure access to the DBGDRAR or DBGDSAR registeris trapped to Hyp mode.If this bit is set to 0 when TDA or TDE is set to 1, behavior is UNPREDICTABLE. This bit resets to 0.[10] TDOSA Trap Debug OS-related register Access:0 Has no effect on accesses to CP14 Debug registers.1 Trap valid Non-secure accesses to CP14 OS-related Debug registers to Hyp mode.When this bit is set to 1, any valid Non-secure CP14 access to the following OS-related Debugregisters is trapped to Hyp mode.• DBGOSLSR.• DBGOSLAR.• DBGOSDLR.• DBGPRCR.If this bit is set to 0 when TDA or TDE is set to 1, behavior is UNPREDICTABLE. This bit resets to 0.[9] TDA Trap Debug Access:0 Has no effect on accesses to CP14 Debug registers.1 Trap valid Non-secure accesses to CP14 Debug registers to Hyp mode.If this bit is set to 0 when TDE is set to 1, behavior is UNPREDICTABLE. This bit resets to 0.If this bit is set to 1, then the TDRA and TDOSA bits must also be set to 1, otherwise the behavioris UNPREDICTABLE.[8] TDE Trap Debug Exceptions:0 Has no effect on Debug exceptions.1 Trap valid Non-secure Debug exceptions to Hyp mode.When this bit is set to 1:• Any Debug exception taken in Non-secure state is trapped to Hyp mode.• The TDRA, TDOSA, and TDA bits must all be set to 1, otherwise behavior isUNPREDICTABLE. This bit resets to 0.[7] HPME Hypervisor Performance Monitors Enable:0 Hyp mode Performance Monitors counters disabled.1 Hyp mode Performance Monitors counters enabled.When this bit is set to 1, access to the Performance Monitors counters that are reserved for usefrom Hyp mode is enabled. For more information, see the description of the HPMN field.The reset value of this bit is UNKNOWN.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-70ID062913Non-Confidential