ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 30 29 28 27 13 12 3 2 0WTWBRAWANumSetsAssociativityLineSizeFigure 4-18 CCSIDR bit assignmentsTable 4-46 shows the CCSIDR bit assignments.Table 4-46 CCSIDR bit assignmentsBits Name Function[31] WT Indicates support for Write-Through:0 Cache level does not support Write-Through.1 Cache level supports Write-Through.[30] WB Indicates support for Write-Back:0 Cache level does not support Write-Back.1 Cache level supports Write-Back.[29] RA Indicates support for Read-Allocation:0 Cache level does not support Read-Allocation.1 Cache level supports Read-Allocation.[28] WA Indicates support for Write-Allocation:0 Cache level does not support Write-Allocation.1 Cache level supports Write-Allocation.[27:13] NumSets Indicates the (number of sets in cache) - 1. Therefore, a value of 0 indicates 1 set in the cache. Thenumber of sets does not have to be a power of 2.[12:3] Associativity Indicates the (associativity of cache) - 1. Therefore, a value of 0 indicates an associativity of 1.The associativity does not have to be a power of 2:0x001 2 ways.0x00F 16 ways.[2:0] LineSize Indicates the (log 2 (number of words in cache line)) - 2:b010 16 words per line.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-49ID062913Non-Confidential