ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System• The coherent masters can share memory in the outer shareable domain only.• L3 cache external to the processor.• The AR channel can issue any command, except for DVM operations.• The AW channel can issue any command.• The system can send snoop commands for outer shareable memory regions on the snoopAC channel.ACE inner coherentThe ACE inner coherent configuration has the following key features:• ACE-compliant with coherent masters on the ACE.• The coherent masters can share memory in the inner or outer shareable domains.• L3 cache external to the processor.• The AR channel can issue any command, including DVM operations.• The AW channel can issue any command.• The system can send DVM or snoop commands for any shareable memory region on thesnoop AC channel.7.7.8 Configuration signalsThe Cortex-A15 MPCore processor implements the following ACE configuration signals:• BROADCASTINNER.• BROADCASTOUTER.• BROADCASTCACHEMAINT.• SYSBARDISABLE.Table 7-5 shows the permitted combinations of these signals and the supported configurationsin the Cortex-A15 MPCore processor.Table 7-5 Supported AXI master bus configurationsSignalFeatureAXI3modeACEnon-coherent,no L3 cacheACEnon-coherent,with L3 cacheACE outercoherentACE innercoherentBROADCASTINNER 0 0 0 0 1BROADCASTOUTER 0 0 0 1 1BROADCASTCACHEMAINTENANCE 0 0 1 1 1SYSBARDISABLE 1 0 0 0 0Note• If the BROADCASTINNER and BROADCASTOUTER signals are deasserted, thisimplies that the Cortex-A15 MPCore processor is in a non-coherent system with nocoherent masters on the ACE interconnect and no transactions can appear on the snoopAC channel.• If any valid requests are issued to the Cortex-A15 MPCore processor on the AC channelwhen BROADCASTINNER and BROADCASTOUTER are both deasserted, theresults are UNPREDICTABLE.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-16ID062913Non-Confidential