ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Chapter 1IntroductionThis chapter introduces the Cortex-A15 MPCore processor and its features. It contains thefollowing sections:• About the Cortex-A15 MPCore processor on page 1-2.• Compliance on page 1-3.• Features on page 1-5.• Interfaces on page 1-6.• Implementation options on page 1-7.• Product documentation and design flow on page 1-9.• Product revisions on page 1-11.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-1ID062913Non-Confidential
Introduction1.1 About the Cortex-A15 MPCore processorThe Cortex-A15 MPCore processor is a high-performance, low-power multiprocessor thatimplements the ARMv7-A architecture. The Cortex-A15 MPCore processor has one to fourCortex-A15 processors in a single multiprocessor device, or MPCore device, with L1 and L2cache subsystems.Figure 1-1 shows an example block diagram of a Cortex-A15 MPCore processor configurationwith four processors.See Components of the processor on page 2-2 for a description of the Cortex-A15 MPCoreprocessor functional components.Cortex-A15 MPCore processorAPB ATB Interrupts TimerEventsDebug andCTITraceGIC(optional)GenericTimerMiscellaneousProcessor 0Processor 1Processor 2Processor 3L1ICacheL1DCacheTLBsL1ICacheL1DCacheTLBsL1ICacheL1DCacheTLBsL1ICacheL1DCacheTLBsSlaveMasterSnoopControlUnitL2 cacheACP ACE Level 2 memory systemFigure 1-1 Example multiprocessor configurationARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-2ID062913Non-Confidential
Page 1 and 2: ®ARM®Cortex -A15 MPCoreProcessorR
Page 3 and 4: ContentsARM Cortex-A15 MPCore Proce
Page 5 and 6: Contents11.4 PMU register descripti
Page 7 and 8: PrefaceAbout this bookThis book is
Page 9 and 10: Preface(continued)Stylemonospace bo
Page 11: PrefaceFeedbackARM welcomes feedbac
Page 15 and 16: Introduction1.2.3 Debug architectur
Page 17 and 18: Introduction1.4 InterfacesThe proce
Page 19 and 20: Introduction• The L2 tag RAM regi
Page 21 and 22: IntroductionThe ARM product deliver
Page 23 and 24: Introduction1.7.5 r1p0 - r2p0The fo
Page 25 and 26: Introduction• Added L1 data TLB s
Page 27 and 28: Functional Description2.1 About the
Page 29 and 30: Functional DescriptionLoad/Store un
Page 31 and 32: Functional Description2.2 Interface
Page 33 and 34: Functional Description2.3 Clocking
Page 35 and 36: Functional DescriptionFigure 2-5 sh
Page 37: Functional DescriptionAll resets ar
Page 41 and 42: Functional DescriptionPowerup reset
Page 43 and 44: Functional Description• nPRESETDB
Page 45 and 46: Functional Description• L2 unifie
Page 47 and 48: Functional DescriptionOn entry into
Page 49 and 50: Functional DescriptionWhen the proc
Page 51 and 52: Functional DescriptionNoteFigure 2-
Page 53 and 54: Functional DescriptionRegional cloc
Page 55 and 56: Functional DescriptionTable 2-3 Val
Page 57 and 58: Functional Description4. Release th
Page 59 and 60: Functional DescriptionDebug power d
Page 61 and 62: Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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Page 392:
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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