ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerUsage constraints There are no usage constraints.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-3 on page 8-8.Figure 8-4 shows the GICD_SPISR bit assignments.31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IRQS[N] statusIRQS[N+1] statusIRQS[N+2] status...IRQS[N+31] statusFigure 8-4 GICD_SPISR bit assignmentsTable 8-8 shows the GICD_SPISR bit assignments.Table 8-8 GICD_SPISR bit assignmentsBits Name Function[31:0] IRQS[N+31:N] Returns the status of the IRQS[223:0] inputs on the Distributor. For each bit:0 IRQS is LOW.1 IRQS is HIGH.Note• The IRQS that a bit refers to depends on its bit position and the base address offset of theGICD_SPISR.• These bits return the actual status of the IRQS signals. The GICD_ISPENDRn andGICD_ICPENDRn can also provide the IRQS status but because you can write to theseregisters, they might not contain the actual status of the IRQS signals.Figure 8-5 on page 8-15 shows the address map that the Distributor provides for the SPIs.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-14ID062913Non-Confidential