ARM Cortex-A15 MPCore Processor Technical Reference Manual

Debug10.4 Debug register descriptionsThis section describes the debug registers. Table 10-1 on page 10-6 provides cross references toindividual registers.10.4.1 Debug ID RegisterThe DBGDIDR characteristics are:PurposeSpecifies:• The version of the Debug architecture that is implemented.• Some features of the debug implementation.Usage constraints There are no usage constraints. See the Debug Device ID Register onpage 10-31 for more information about the debug implementation.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-2 shows the DBGDIDR bit assignments.31 28 27 24 23 20 19 16 15 14 13 12 11 8 7 4 3 0WRPs BRPs CTX_CMPs Version Reserved VariantRevisionDEVID_impnSUHD_impSE_impPCSRFigure 10-2 DBGDIDR bit assignmentsTable 10-2 shows the DBGDIDR bit assignments.Table 10-2 DBGDIDR bit assignmentsBits Name Function[31:28] WRPs The number of Watchpoint Register Pairs (WRPs) implemented. The number of implemented WRPs isone more than the value of this field.0x3 The processor implements 4 WRPs.[27:24] BRPs The number of Breakpoint Register Pairs (BRPs) implemented. The number of implemented BRPs is onemore than the value of this field.0x5 The processor implements 6 BRPs.[23:20] CTX_CMPs The number of BRPs that can be used for Context matching. This is one more than the value of this field.0x1 The processor implements two Context matching breakpoints, that is, breakpoints 4 and 5.[19:16] Version The Debug architecture version.0x5 The processor implements ARMv7, v7.1 Debug architecture.[15] DEVID_imp Debug Device ID Register bit.1 DBGDEVID is implemented.[14] nSUHD_imp Secure User Halting Debug not implemented bit.1 The processor does not implement Secure User Halting Debug.[13] PCSR_imp Program Counter Sampling Register (DBGPCSR) implemented as register 33 bit.1 DBGPCSR is implemented as register 33.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-10ID062913Non-Confidential