ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System ControlTable 4-79 L2MERRSR bit assignments (continued)Bits Name Function[31] Valid Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, itremains set until the register is written.The reset value is 0.[30:24] RAMID RAM Identifier. Indicates the RAM where the first memory error occurred:0x10 L2 tag RAM.0x11 L2 data RAM.0x12 L2 snoop tag RAM.0x14 L2 dirty RAM.[23:22] - Reserved, RAZ/WI.[21:18] CPUID/Way Indicates which processor and way of the RAM where the first memory error occurred.For L2 tag, data, and dirty RAMs, bits[21:18] indicate one of 16 ways, from way 0 to way 15.b0000 CPU0 tag, way 0.b0001 CPU0 tag, way 1.b0010 CPU1 tag, way 0.b0011 CPU1 tag, way 1.b0100 CPU2 tag, way 0.b0101 CPU2 tag, way 1.b0110 CPU3 tag, way 0.b0111 CPU3 tag, way 1.For L2 snoop tag RAM:• Bits[20:19] indicate which processor of the L1 tag RAM.• Bit[18] indicates which way of the tag RAM.[17:0] Index Indicates the index address of the first memory error.Note• If two or more memory errors in the same RAM occur in the same cycle, only one erroris reported.• If two or more first memory error events from different RAMs occur in the same cycle,one of the errors is selected arbitrarily, while the Other error count field is onlyincremented by one.• If two or more memory error events from different RAMs, that do not match the RAMID,bank, way, or index information in this register while the sticky Valid bit is set, occur inthe same cycle, the Other error count field is only incremented by one.To access the L2MERRSR, read or write the CP15 register with:MRRC p15, 1, , , c15; Read L2 Memory Error Syndrome RegisterMCCR p15, 1, , , c15; Write L2 Memory Error Syndrome RegisterARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-110ID062913Non-Confidential
Chapter 5Memory Management UnitThis chapter describes the Memory Management Unit (MMU). It contains the followingsections:• About the MMU on page 5-2.• TLB organization on page 5-3.• TLB match process on page 5-4.• Memory access sequence on page 5-5.• MMU enabling and disabling on page 5-7.• Intermediate table walk caches on page 5-8.• External aborts on page 5-10.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-1ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
Page 134 and 135: System ControlTable 4-53 ACTLR bit
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Page 138 and 139: System ControlUsage constraints The
Page 140 and 141: System Control• The L2 internal a
Page 142 and 143: System Control31 30 29 28 27 26 25
Page 144 and 145: System ControlTable 4-58 shows the
Page 146 and 147: System ControlUsage constraints The
Page 148 and 149: System ControlTable 4-59 HCPTR bit
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Page 154 and 155: System ControlTable 4-63 IFSR bit a
Page 156 and 157: System ControlConfigurationsAvailab
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Page 162 and 163: System Control• Only accessible f
Page 164 and 165: System Control31 0DataFigure 4-40 I
Page 168 and 169: System ControlThe data returned fro
Page 170 and 171: System ControlThe data returned fro
Page 174 and 175: System Control4.3.60 L2 Auxiliary C
Page 176 and 177: System ControlTable 4-74 L2ACTLR bi
Page 178 and 179: System Control• Is only accessibl
Page 186 and 187: Memory Management Unit5.1 About the
Page 188 and 189: Memory Management Unit5.3 TLB match
Page 190 and 191: Memory Management Unit• The TLB t
Page 192 and 193: Memory Management Unit5.6 Intermedi
Page 194 and 195: Memory Management Unit5.7 External
Page 196 and 197: Level 1 Memory System6.1 About the
Page 198 and 199: Level 1 Memory System6.3 L1 instruc
Page 200 and 201: Level 1 Memory System6.4 L1 data me
Page 202 and 203: Level 1 Memory SystemL1 or L2 cache
Page 204 and 205: Level 1 Memory SystemExternal globa
Page 206 and 207: Level 1 Memory System6.5 Program fl
Page 208 and 209: Level 1 Memory SystemReset:• Disa
Page 210 and 211: Chapter 7Level 2 Memory SystemThis
Page 212 and 213: Level 2 Memory System7.2 Cache orga
Page 214 and 215: Level 2 Memory System7.2.5 Register
Page 216 and 217: Level 2 Memory SystemNote• The L2
Page 218 and 219: Level 2 Memory System7.4 L2 cache p
Page 220 and 221: Level 2 Memory System7.6 Asynchrono
Page 222 and 223: Level 2 Memory SystemFor certain tr
Page 224 and 225: Level 2 Memory System7.7.6 Snoop fi
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Page 228 and 229: Chapter 8Generic Interrupt Controll
Page 230 and 231: Generic Interrupt Controller8.2 GIC
Page 232 and 233: Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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