ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionOn entry into WFI low-power state, STANDBYWFI for that processor is asserted. Assertion ofSTANDBYWFI guarantees that the processor is in idle and low power state. STANDBYWFIcontinues to assert even if the clocks in the processor are temporarily enabled because of an L2snoop request, cache, TLB, and BTB maintenance operation or an APB access.Figure 2-12 shows the upper bound for the STANDBYWFI deassertion timing after theassertion of nIRQ or nFIQ inputs.CLK10 CLK cycles maximumnIRQ or nFIQSTANDBYWFIFigure 2-12 STANDBYWFI deassertion timingProcessor Wait for EventWait for Event is a feature of the ARMv7-A architecture that uses a locking mechanism basedon events to put the processor in a low power state by disabling most of the clocks in theprocessor while keeping the processor powered up. This reduces the power drawn to the staticleakage current, leaving a small clock power overhead to enable the processor to wake up fromWFE low-power state.A processor enters into WFE low-power state by executing the WFE instruction. When executingthe WFE instruction, the processor waits for all instructions in the processor to complete beforeentering the idle or low power state. The WFE instruction ensures that all explicit memoryaccesses occurred before the WFE instruction in program order, have completed.While the processor is in WFE low-power state, the clocks in the processor are temporarilyenabled without causing the processor to exit WFE low-power state, when any of the followingevents are detected:• An L2 snoop request that must be serviced by the processor L1 data cache.• A cache, TLB or BTB maintenance operation that must be serviced by the processor L1instruction cache, data cache, instruction TLB, data TLB, or BTB.• An APB access to the debug or trace registers residing in the processor power domain.Exit from WFE low-power state occurs when the processor detects a reset, the assertion of theEVENTI input signal, or one of the WFI wake up events as described in the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition.On entry into WFE low-power state, STANDBYWFE for that processor is asserted. Assertionof STANDBYWFE guarantees that the processor is in idle and low power state.STANDBYWFE continues to assert even if the clocks in the processor are temporarily enabledbecause of an L2 snoop request, cache, TLB, and BTB maintenance operation or an APB access.The upper bound for the STANDBYWFE deassertion timing after the assertion of nIRQ ornFIQ inputs is identical to STANDBYWFI as shown in Figure 2-12.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-22ID062913Non-Confidential