ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-74 L2ACTLR bit assignments (continued)Bits Name Function[26] a Enable L2, GIC, and Timerregional clock gates[25] Enable replay threshold singleissue - all tag banksEnables L2, GIC, and Timer regional clock gates:0 Disables the L2, GIC, and Timer regional clock gates. This is the resetvalue.1 Enables the L2, GIC, and Timer regional clock gates for additional clockgating. When this bit is set, the regional clock gates can gate-off theclock and potentially reduce dynamic power dissipation.Enables replay threshold single issue for all tag banks when L2 arbitration replaythreshold is reached:0 Disables single issue across tag banks when L2 arbitration replaythreshold is reached. This is the reset value.1 Enables single issue across tag banks when L2 arbitration replaythreshold is reached.[24:17] - Reserved, RAZ/WI.[16] a Enable replay threshold singleissue - current tag bank[15] Enable CPU WFI retentionmode a[14] Enable UniqueClean evictionswith data a[13] Disable SharedClean datatransfers a[12] Disable multiple outstandingWriteClean/WriteBack/Evictsusing the same AWID a[11] Disable Data SynchronizationBarrier (DSB) with noDistributed Virtual Memory(DVM) synchronization a[10] Disable Non-secure debugarray readEnables replay threshold single issue for current tag bank:0 Disables replay threshold single issue. This is the reset value.1 Enables replay threshold single issue. If 32 consecutive transactions ona tag bank replay, then single issue is forced until a transactionsuccessfully passes hazard checking.Enables CPU WFI retention mode:0 Disables CPU WFI retention mode. This is the reset value.1 Enables CPU WFI retention mode.Enables UniqueClean evictions with data:0 Disables UniqueClean evictions with data. This is the reset value.1 Enables UniqueClean evictions with data.Disables SharedClean data transfers:0 Enables SharedClean data transfers. This is the reset value.1 Disables SharedClean data transfers.Disables multiple outstanding WriteClean/WriteBack/Evicts using the same AWID:0 Enables multiple outstanding WriteClean/WriteBack/Evicts using thesame AWID. This is the reset value.1 Disables multiple outstanding WriteClean/WriteBack/Evicts using thesame AWID.Disables DSB with no DVM synchronization:0 Enables DSB with no DVM synchronization. This is the reset value.1 Disables DSB with no DVM synchronization.Disables Non-secure debug array read:0 Enables Non-secure debug array read access to Non-secure memory.This is the reset value.1 Disables Non-secure debug array read access.[9] - Reserved, RAZ/WI.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-102ID062913Non-Confidential