ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-6 on page 4-6.Figure 4-36 shows the HADFSR bit assignments.31 30 24 23 22 18 170RAM IDBank/WayIndexValidL2 ErrorFigure 4-36 HADFSR bit assignmentsTable 4-67 shows the HADFSR bit assignments.Table 4-67 HADFSR bit assignmentsBits Name Function[31] Valid Valid bit. This field indicates that an L1 or L2 ECC double-bit error has occurred:0 No L1 or L2 ECC double-bit error occurred.1 An L1 or L2 ECC double-bit error occurred.[30:24] RAM ID RAM Identifier. This field indicates which RAM, the L1 ECC double-bit error occurred in:0x8L1 tag RAM.0x9L1 data RAM.If an L2 ECC double-bit error occurred, this field returns 0.[23] L2 Error L2 Error bit. This field indicates an L2 ECC double-bit error occurred:0 No L2 ECC double-bit error occurred.1 An L2 ECC double-bit error occurred.[22:18] Bank/Way Bank/Way bit. This field indicates which bank or way of the RAM, the L1 ECC double-bit erroroccurred in. If an L2 ECC double-bit error occurred, this field returns 0.[17:0] Index Index. This field indicates the index address of the RAM, the L1 ECC double-bit error occurredin. If an L2 ECC double-bit error occurred, this field returns 0.To access the HADFSR, read or write the CP15 register with:MRC p15, 4, , c5, c1, 0; Read Hyp Auxiliary Data Fault Status Syndrome RegisterMCR p15, 4, , c5, c1, 0; Write Hyp Auxiliary Data Fault Status Syndrome Register4.3.45 Hyp Auxiliary Instruction Fault Syndrome RegisterThe processor does not implement HAIFSR, so this register is always RAZ/WI.4.3.46 Hyp Syndrome RegisterThe HSR characteristics are:PurposeHolds syndrome information for an exception taken to Hyp mode.Usage constraints The HSR is:• A read/write register.• Only accessible from Hyp mode or from Monitor mode whenSCR.NS is 1ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-83ID062913Non-Confidential