ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional Description2.4 Power managementThe Cortex-A15 MPCore processor provides mechanisms and support to control both dynamicand static power dissipation. The following sections describe:• Dynamic power management.• Power domains on page 2-28.• Power modes on page 2-29.• Event communication using WFE and SEV instructions on page 2-37.2.4.1 Dynamic power managementThis section describes the following dynamic power management features in the Cortex-A15MPCore processor:• Processor Wait for Interrupt.• Processor Wait for Event on page 2-22.• L2 Wait for Interrupt on page 2-23.• Processor retention in WFI and WFE low-power state on page 2-24.• NEON and VFP clock gating on page 2-27.• L2 control and tag banks clock gating on page 2-27.• Regional clock gating on page 2-28.Processor Wait for InterruptWait for Interrupt is a feature of the ARMv7-A architecture that puts the processor in a lowpower state by disabling most of the clocks in the processor while keeping the processorpowered up. This reduces the power drawn to the static leakage current, leaving a small clockpower overhead to enable the processor to wake up from WFI low-power state.A processor enters into WFI low-power state by executing the WFI instruction.When executing the WFI instruction, the processor waits for all instructions in the processor toretire before entering the idle or low power state. The WFI instruction ensures that all explicitmemory accesses occurred before the WFI instruction in program order, have retired. Forexample, the WFI instruction ensures that the following instructions received the required data orresponses from the L2 memory system:• Load instructions.• Cache and TLB maintenance operations.• Store exclusives instructions.In addition, the WFI instruction ensures that store instructions have updated the cache or havebeen issued to the L2 memory system.While the processor is in WFI low-power state, the clocks in the processor are temporarilyenabled without causing the processor to exit WFI low-power state, when any of the followingevents are detected:• An L2 snoop request that must be serviced by the processor L1 data cache.• A cache, TLB or BTB maintenance operation that must be serviced by the processor L1instruction cache, data cache, instruction TLB, data TLB, or BTB.• An APB access to the debug or trace registers residing in the processor power domain.Exit from WFI low-power state occurs when the processor detects a reset or one of the WFIwake up events as described in the ARM ® Architecture Reference Manual ARMv7-A andARMv7-R edition.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-21ID062913Non-Confidential