ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlOp1 CRm Op2 Name Reset DescriptionTable 4-2 c0 register summary (continued)3 ID_ISAR3 0x11112131 Instruction Set Attribute Register 3 on page 4-444 ID_ISAR4 0x10011142 Instruction Set Attribute Register 4 on page 4-465 ID_ISAR5 0x00000000 Instruction Set Attribute Register 5 on page 4-481 c0 0 CCSIDR UNK Cache Size ID Register on page 4-481 CLIDR 0x0A200023 Cache Level ID Register on page 4-507 AIDR 0x00000000 Auxiliary ID Register on page 4-512 c0 0 CSSELR UNK Cache Size Selection Register on page 4-514 c0 0 VPIDR - c Virtualization Processor ID Register on page 4-525 VMPIDR - d Virtualization Multiprocessor ID Register on page 4-53a. The reset value depends on the primary input, IMINLN. The value shown in Table 4-2 on page 4-4 assumes IMINLNis set to 1.b. The reset value depends on the primary input, CLUSTERID, and the number of configured processors in the MPCoredevice.c. The reset value is the value of the Main ID Register.d. The reset value is the value of the Multiprocessor Affinity Register.4.2.2 c1 registersTable 4-3 shows the 32-bit wide CP15 system control registers when CRn is c1.Op1 CRm Op2 Name Reset Description0 c0 0 SCTLR 0x00C50078 a System Control Register on page 4-541 ACTLR 0x00000000 Auxiliary Control Register on page 4-572 CPACR 0x00000000 b Coprocessor Access Control Register on page 4-62c1 0 SCR 0x00000000 Secure Configuration Register on page 4-63Table 4-3 c1 register summary1 SDER UNK Secure Debug Enable Register, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition2 NSACR 0x00000000 c Non-Secure Access Control Register on page 4-654 c0 0 HSCTLR UNK Hyp System Control Register on page 4-671 HACTLR UNK Hyp Auxiliary Control Register on page 4-69c1 0 HCR 0x00000000 Hyp Configuration Register, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition1 HDCR 0x00000006 d Hyp Debug Configuration Register on page 4-692 HCPTR 0x000033FF e Hyp Coprocessor Trap Register on page 4-713 HSTR 0x00000000 Hyp System Trap Register, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition7 HACR UNK Hyp Auxiliary Configuration Register on page 4-74ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-5ID062913Non-Confidential