ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-78 shows the CPUMERRSR bit assignments.Table 4-78 CPUMERRSR bit assignmentsBits Name Function[63] Fatal Fatal bit. This bit is set to 1 on the first memory error that caused a Data Abort. It is a sticky bit sothat after it is set, it remains set until the register is written.The reset value is 0.[62:48] - Reserved, RAZ/WI.[47:40] Other error count This field is set to 0 on the first memory error and is incremented on any memory error that doesnot match the RAMID, bank, way, or index information in this register while the sticky Valid bitis set.The reset value is 0.[39:32] Repeat error count This field is set to 0 on the first memory error and is incremented on any memory error that exactlymatches the RAMID, bank, way or index information in this register while the sticky Valid bit isset.The reset value is 0.[31] Valid Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, itremains set until the register is written.The reset value is 0.[30:24] RAMID RAM Identifier. Indicates the RAM, the first memory error occurred in:0x00 L1-I tag RAM.0x01 L1-I data RAM.0x02 L1-I BTB RAM.0x08 L1-D tag RAM.0x09 L1-D data RAM.0x18 L2 TLB RAM.[23] - Reserved, RAZ/WI.[22:18] Bank/Way Indicates the bank or way of the RAM where the first memory error occurred.[17:0] Index Indicates the index address of the first memory error.Note• If two or more memory errors in the same RAM occur in the same cycle, only one erroris reported.• If two or more first memory error events from different RAMs occur in the same cycle,one of the errors is selected arbitrarily, while the Other error count field is onlyincremented by one.• If two or more memory error events from different RAMs, that do not match the RAMID,bank, way, or index information in this register while the sticky Valid bit is set, occur inthe same cycle, the Other error count field is only incremented by one.To access the CPUMERRSR, read or write the CP15 register with:MRRC p15, 0, , , c15; Read CPU Memory Error Syndrome RegisterMCCR p15, 0, , , c15; Write CPU Memory Error Syndrome RegisterARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-108ID062913Non-Confidential