ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.1 About the L2 memory systemThe L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop ControlUnit (SCU), connecting up to four processors within a Cortex-A15 MPCore device. The L2memory system also interfaces with an AMBA 4 (ACE) interconnect and an AcceleratorCoherency Port (ACP) that is implemented as an AXI3 slave interface.The features of the L2 memory system include:• Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB.• Fixed line length of 64 bytes.• Physically indexed and tagged cache.• 16-way set-associative cache structure.• Banked pipeline structures.• Strictly enforced inclusion property with L1 data caches.• Random cache-replacement policy.• Configurable 64-bit or 128-bit wide ACE with support for multiple outstanding requests.• Configurable 64-bit or 128-bit wide ACP with support for multiple incoming requests.• Duplicate copies of the L1 data cache directories for coherency support.• Optional Error Correction Code (ECC) support.• Optional hardware prefetch support.• Software-programmable variable latency RAMs.• Register slice support for large L2 cache sizes to minimize impact on routing delays.• MBIST support.NoteThe Cortex-A15 MPCore processor does not support TLB or cache lockdown.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-2ID062913Non-Confidential