ARM Cortex-A15 MPCore Processor Technical Reference Manual

Introduction• The L2 tag RAM register slice option adds register slices to the L2 tag RAMs. The L2data RAM register slice option adds register slices to the L2 data RAMs. Table 1-2 onpage 1-8 lists valid combinations of the L2 tag RAM and L2 data RAM register sliceoptions.• If L2 arbitration register slice is included, an additional pipeline stage for the CPU-L2arbitration logic interface is added to the L2 arbitration logic.• If L2 logic idle clock gating is present, most of the L2 logic is dynamically clock gatedwith a different clock than the GIC and Generic Timer. If L2 logic idle clock gating is notpresent, the L2 logic is not dynamically clock gated, and shares the same clock as the GICand Generic Timer. The clock gate generator for the L2 logic is also removed. Havingdynamic clock gating of the L2 logic can provide lower power dissipation, but at the costof a more complex clock tree implementation.• If regional clock gating is present, an additional level of clock gating occurs for severallogic blocks such as the register banks. Having regional clock gating can potentiallyprovide lower power dissipation, but at the cost of a more complex clock treeimplementation.Table 1-2 shows valid combinations of the L2 tag RAM and L2 data RAM register slice options.Table 1-2 Valid combinations of L2 tag and data RAM register sliceL2 tag RAMregister sliceL2 data RAMregister slice0 00 10 21 11 2ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-8ID062913Non-Confidential