ARM Cortex-A15 MPCore Processor Technical Reference Manual

Introduction1.3 FeaturesThe Cortex-A15 MPCore processor includes the following features:• Full implementation of the ARMv7-A architecture instruction set with the architectureextensions listed in Compliance on page 1-3.• Superscalar, variable-length, out-of-order pipeline.• Dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer(GHB), a return stack, and an indirect predictor.• Three separate 32-entry fully-associative Level 1 (L1) Translation Look-aside Buffers(TLBs), one for instruction, one for data loads, and one for data stores.• 4-way set-associative 512-entry Level 2 (L2) TLB in each processor.• Fixed 32KB L1 instruction and data caches.• Shared L2 cache of 512KB, 1MB, 2MB, or 4MB configurable size.• Optional Error Correction Code (ECC) protection for L1 data cache and L2 cache, andparity protection for L1 instruction cache.• AMBA 4 AXI Coherency Extensions (ACE) master interface.• Accelerator Coherency Port (ACP) that is implemented as an AXI3 slave interface.• Program Trace Macrocell (PTM) based on version 1.1 of the Program Flow Trace(PFTv1.1) architecture.• Performance Monitor Unit (PMU) based on PMUv2 architecture.• Cross trigger interfaces for multi-processor debugging.• VFP component only or optionally implemented VFP and NEON components.• Optional Generic Interrupt Controller (GIC) that supports up to 224 Shared PeripheralInterrupts (SPIs).• ARM generic 64-bit timers for each processor.• Support for power management with multiple power domains.1.3.1 Test featuresThe Cortex-A15 MPCore processor provides several test signals that enable the use of bothATPG and MBIST to test the Cortex-A15 MPCore processor and its memory arrays. SeeAppendix A Signal Descriptions for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 1-5ID062913Non-Confidential