ARM Cortex-A15 MPCore Processor Technical Reference Manual

Performance Monitor UnitTable 11-3 shows the PMCR bit assignments.Table 11-3 PMCR bit assignmentsBits Name Function[31:24] IMP Implementer code:0x41 ARM.This is a read-only field.[23:16] IDCODE Identification code:0x0F Cortex-A15.This is a read-only field.[15:11] N Number of event counters. In Non-secure modes other than Hyp mode, this field reads the valueof HDCR.HPMN. See Hyp Debug Configuration Register on page 4-69. In Secure state and Hypmode, this field returns 0x6 that indicates the number of counters implemented.This is a read-only field.[10:6] - Reserved, UNK/SBZP.[5] DP Disable PMCCNTR when event counting is prohibited:0 Cycle counter operates regardless of the non-invasive debug authenticationsettings. This is the reset value.1 Cycle counter is disabled if the non-invasive debug is not permitted and enabled.This bit is read/write. For more information on prohibited regions, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition.[4] X Export enable. This bit permits events to be exported to another debug device, such as a tracemacrocell, over an event bus:0 Export of events is disabled. This is the reset value.1 Export of events is enabled.This bit is read/write and does not affect the generation of Performance Monitors interrupts, thatcan be implemented as a signal exported from the processor to an interrupt controller.[3] D Clock divider:0 When enabled, PMCCNTR counts every clock cycle. This is the reset value.1 When enabled, PMCCNTR counts every 64 clock cycles.This bit is read/write.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-9ID062913Non-Confidential