ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace MacrocellTable 12-5 ETMCR bit assignments (continued)Bits Name Function[15:14] ContextIDsize The possible value of this field are:b00No Context ID tracing.b01One byte traced, Context ID bits[7:0].b10Two bytes traced, Context ID bits[15:0].b11Four bytes traced, Context ID bits[31:0].The reset value is 0.NoteThe PTM traces only the number of bytes specified, even if the new ContextID value is larger than this.[13] - SBZP.[12] CycleAccurate Set this bit to 1 to enable cycle-accurate tracing. The reset value is 0.[11] - SBZP.[10] ProgBit Programming bit. You must set this bit to 1 to program the PTM, and clear itto 0 when programming is complete. The reset value is 1.[9] Debug request control When this bit is set to 1 and the trigger event occurs, the DBGRQ output isasserted until DBGACK is observed. This enables a debugger to force theprocessor into Debug state. The reset value is 0.[8] BranchBroadcast Set this bit to 1 to enable branch broadcasting. Branch broadcasting traces theaddresses of direct branch instructions. You must not set this bit to 1 if bit[29]of this register is set to 1 to enable use of the return stack. Behavior isUNPREDICTABLE if you enable both use of the return stack and branchbroadcasting. The reset value is 0.[7] Stall processor RAZ. This bit is not implemented.[6:1] - SBZP.[0] Powerdown A pin controlled by this bit enables the PTM power to be controlled externally.The external pin is PTMPWRDOWN, or inverted as PTMPWRUP.This bit must be cleared by the trace software tools at the beginning of a debugsession. When this bit is set to 1, the PTM must be powered down and disabled,and then operated in a low power mode with all clocks stopped.When this bit is set to 1, writes to some registers and fields might be ignored.You can always write to the following registers and fields:• ETMCR, bit[0] and bits[27:25].• ETMLAR.• ETMCLAIMSET.• ETMCLAIMCLR.• ETMOSLAR.When ETMCR is written with this bit set to 1, writes to bits other thanbits[27:25, 0] might be ignored. The reset value is 1.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-15ID062913Non-Confidential