ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-44 ID_ISAR3 bit assignments (continued)Bits Name Function[11:8] SVC_instrs Indicates the supported SVC instructions:0x1Processor supports SVC instruction.NoteThe SVC instruction was called the SWI instruction in previous versions of the ARM architecture.[7:4] SIMD_instrs Indicates the supported Single Instruction Multiple Data (SIMD) instructions.0x3Processor supports:• SSAT and USAT instructions, and the Q bit in the PSRs.• PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX,SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8,SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16,UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8,USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and the GE[3:0]bits in the PSRs.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[3:0] Saturate_instrs Indicates the supported Saturate instructions:0x1Processor supports QADD, QDADD, QDSUB, QSUB and the Q bit in the PSRs.To access the ID_ISAR3, read the CP15 register with:MRC p15, 0, , c0, c2, 3 ; Read Instruction Set Attribute Register 34.3.19 Instruction Set Attribute Register 4The ID_ISAR4 characteristics are:PurposeProvides information about the instruction set that the processor supports.Usage constraints The ID_ISAR4 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-17 on page 4-47 shows the ID_ISAR4 bit assignments.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-46ID062913Non-Confidential