ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-77 shows the CBAR bit assignments.Table 4-77 CBAR bit assignmentsBits Name Function[31:15] PERIPHBASE[31:15] The primary input PERIPHBASE[31:15] determines the reset value.[11:8] - Reserved, UNK/SBZP.[7:0] PERIPHBASE[39:32] The primary input PERIPHBASE[39:32] determines the reset value.To access the CBAR, read the CP15 register with:MRC p15, 4, , c15, c0, 0; Read Configuration Base Address Register4.3.64 CPU Memory Error Syndrome RegisterThe CPUMERRSR characteristics are:PurposeHolds the number of memory errors that have occurred in the followingL1 and L2 RAMs:• L1-I tag RAM.• L1-I data RAM.• L1-I BTB RAM.• L1-D tag RAM.• L1-D data RAM.• L2 TLB RAM.Usage constraints The CPUMERRSR:• Is a 64-bit read/write register.• Is Common to the Secure and Non-secure states.• Is only accessible from PL1 or higher.• A write of any value to the register updates the register to 0x0.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-15 on page 4-13.Figure 4-63 shows the CPUMERRSR bit assignments.FatalReservedOther error countRepeat error count63 62 48 47 40 39 3231 30 24 23 22 18 17 0RAMIDBank/WayIndexValidReservedFigure 4-63 CPUMERRSR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-107ID062913Non-Confidential