ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Level 2 Memory SystemTable 7-6 shows the key features in each of the supported ACE configurations.Table 7-6 Supported features in the ACE configurationsFeaturesConfigurationAXI3 modeACEnon-coherent,no L3 cacheACEnon-coherent,with L3 cacheACE outercoherentACE innercoherentAXI3 compliance Y N N N NACE compliance N Y Y Y YBarriers on AR channel N Y Y Y YCaches on AR channel N N Y Y YSnoops on AC channel N N N Y YCoherent requests on AR or AWchannelN N N Y YDVM requests on AR channel N N N N YARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-17ID062913Non-Confidential
Level 2 Memory System7.8 Accelerator Coherency PortAccelerator Coherency Port (ACP) is implemented as an AXI3 slave interface that supports thefollowing features:• Configurable 64-bit or 128-bit read and write interfaces.• All burst types such as INCR, WRAP, or FIXED.Note• ACP does not support fixed addressing mode to Normal Memory.• The Cortex-A15 MPCore processor does not support a 64-bit ACE with a 128-bit ACP.This section describes ACP in:• ACP L2 memory interface attributes.• Burst support.• ACP user bits.7.8.1 ACP L2 memory interface attributesTable 7-7 shows the ACP L2 memory interface attributes for the Cortex-A15 MPCoreprocessor. The table lists the maximum possible values for the read and write issuingcapabilities.Attribute Value DescriptionTable 7-7 ACP L2 memory interface attributesACP read acceptance capability 8 4 requests buffered and 4 requests actively being processed.ACP write acceptance capability 8 4 requests buffered and 4 requests actively being processed.7.8.2 Burst supportACP supports a maximum burst lengths of 16 over AXI3. The L2 memory system breaks uptransactions on a cache line boundary, creating additional requests to the L2 pipeline, andpossibly the ACE for L2 cache misses. Ordering is maintained for the requests, and theresponses are generated in the appropriate order on the ACP. For reads, data must be returnedin the order of the original burst received. For writes to Strongly-ordered memory, the BRESPis generated from the final destination. All other BRESPs are generated on the last write datapacket received on the ACP interface.The Cortex-A15 MPCore processor supports fixed burst type transactions only to Device andStrongly-ordered memory.7.8.3 ACP user bitsBecause ACP transactions can be cached in the L2 cache, and the L2 observes inner memorypage attributes, these must be supplied on the ACP.To pass the outer page attributes, use the ARCACHE[3:0] and AWCACHE[3:0] fields.To pass the inner page attributes, use the ARUSER[5:2] and AWUSER[5:2] fields. To pass theinner shareable attribute, use ARUSER[1] and AWUSER[1]. To pass the outer shareableattribute, use ARUSER[0] and AWUSER[0]. See Appendix A Signal Descriptions for moreinformation.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-18ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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Page 180 and 181: System ControlTable 4-76 shows the
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Page 184 and 185: System ControlTable 4-79 L2MERRSR b
Page 186 and 187: Memory Management Unit5.1 About the
Page 188 and 189: Memory Management Unit5.3 TLB match
Page 190 and 191: Memory Management Unit• The TLB t
Page 192 and 193: Memory Management Unit5.6 Intermedi
Page 194 and 195: Memory Management Unit5.7 External
Page 196 and 197: Level 1 Memory System6.1 About the
Page 198 and 199: Level 1 Memory System6.3 L1 instruc
Page 200 and 201: Level 1 Memory System6.4 L1 data me
Page 202 and 203: Level 1 Memory SystemL1 or L2 cache
Page 204 and 205: Level 1 Memory SystemExternal globa
Page 206 and 207: Level 1 Memory System6.5 Program fl
Page 208 and 209: Level 1 Memory SystemReset:• Disa
Page 210 and 211: Chapter 7Level 2 Memory SystemThis
Page 212 and 213: Level 2 Memory System7.2 Cache orga
Page 214 and 215: Level 2 Memory System7.2.5 Register
Page 216 and 217: Level 2 Memory SystemNote• The L2
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Page 220 and 221: Level 2 Memory System7.6 Asynchrono
Page 222 and 223: Level 2 Memory SystemFor certain tr
Page 224 and 225: Level 2 Memory System7.7.6 Snoop fi
Page 228 and 229: Chapter 8Generic Interrupt Controll
Page 230 and 231: Generic Interrupt Controller8.2 GIC
Page 232 and 233: Generic Interrupt Controller8.2.4 I
Page 234 and 235: Generic Interrupt Controller8.3 GIC
Page 236 and 237: Generic Interrupt ControllerOffset
Page 238 and 239: Generic Interrupt ControllerTable 8
Page 240 and 241: Generic Interrupt ControllerPrivate
Page 242 and 243: Generic Interrupt Controller0x1D043
Page 244 and 245: Generic Interrupt ControllerThe Cor
Page 246 and 247: Generic Interrupt ControllerTable 8
Page 248 and 249: Generic Interrupt Controller8.3.8 V
Page 250 and 251: Generic Timer9.1 About the Generic
Page 252 and 253: Generic Timer9.3 Generic Timer prog
Page 254 and 255: Chapter 10DebugThis chapter describ
Page 256 and 257: Debug• Operating systems.• Hard
Page 258 and 259: DebugnPRESETDBGThis signal initiali
Page 260 and 261: DebugTable 10-1 CP14 debug register
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Page 264 and 265: DebugTable 10-2 DBGDIDR bit assignm
Page 266 and 267: DebugTable 10-4 shows the DBGDRCR b
Page 268 and 269: DebugConfigurationsAttributesThe pr
Page 270 and 271: DebugTable 10-8 DBGBCR bit assignme
Page 272 and 273: DebugTable 10-10 shows the DBGWCR b
Page 274 and 275: Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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