ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerPrivate Peripheral Interrupt Status RegisterThe GICD_PPISR characteristics are:PurposeEnables a Cortex-A15 MPCore processor to access the status of the PPIinputs on the Distributor.Usage constraints A processor can only read the status of its own PPI and therefore cannotread the status of the PPI for other processors.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-3 on page 8-8.Figure 8-3 shows the GICD_PPISR bit assignments.31 16 15 14 13 12 11 10 9 8 0ReservedReservedPPI3 statusPPI2 statusPPI1 statusPPI0 statusPPI6 statusPPI5 statusPPI4 statusFigure 8-3 GICD_PPISR bit assignmentsTable 8-7 shows the GICD_PPISR bit assignments.Table 8-7 GICD_PPISR bit assignmentsBits Name Description[31:16] - Reserved, RAZ[15:9] PPI status Returns the status of the PPI[6:0] inputs on the Distributor:PPI6 Virtual Maintenance Interrupt.PPI5 Hypervisor timer event.PPI4 Virtual timer event.PPI3 nIRQ.PPI2 Non-secure physical timer event.PPI1 Secure physical timer event.PPI0 nFIQ.PPI0-5 Active-LOW level-sensitive.PPI6 Active-HIGH level-sensitive.NoteThese bits return the actual status of the PPI[6:0] signals. The GICD_ISPENDRn andGICD_ICPENDRn can also provide the PPI[6:0] status but because you can write to theseregisters, they might not contain the true status of the PPI[6:0] signals.[8:0] - Reserved, RAZShared Peripheral Interrupt Status RegistersThe GICD_SPISR characteristics are:PurposeEnables a Cortex-A15 MPCore processor to access the status of theIRQS[223:0] inputs on the Distributor.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-13ID062913Non-Confidential