ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-40 ID_MMFR3 bit assignments (continued)Bits Name Function[11:8] Branch predictor maintenance Indicates the supported branch predictor maintenance operations.0x2Processor supports:• Invalidate all branch predictors.• Invalidate branch predictors by MVA.[7:4] Cache maintenance by set/way Indicates the supported cache maintenance operations by set/way.0x1Processor supports:• Invalidate data cache by set/way.• Clean data cache by set/way.• Clean and invalidate data cache by set/way.[3:0] Cache maintenance by MVA Indicates the supported cache maintenance operations by MVA.0x1Processor supports:• Invalidate data cache by MVA.• Clean data cache by MVA.• Clean and invalidate data cache by MVA.• Invalidate instruction cache by MVA.• Invalidate all instruction cache entries.To access the ID_MMFR3, read the CP15 register with:MRC p15, 0, , c0, c1, 7; Read Memory Model Feature Register 34.3.15 Instruction Set Attribute Register 0The ID_ISAR0 characteristics are:PurposeProvides information about the instruction set that the processor supports.Usage constraints The ID_ISAR0 is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-13 shows the ID_ISAR0 bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0ReservedDivide_instrsDebug_instrsCoproc_instrsCmpBranch_instrsBitfield_instrsBitCount_instrsSwap_instrsFigure 4-13 ID_ISAR0 bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-40ID062913Non-Confidential