ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Controla. The reset value depends on primary inputs, CFGTE, CFGEND, and VINITHI. The value shown in Table 4-3 on page 4-5 assumes thesesignals are set to zero.b. The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x00000000. If VFPis implemented but NEON is not implemented, the reset value is 0x80000000. If VFP and NEON are not implemented, the reset value is0x00000000.c. The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x00000000. If VFPis implemented but NEON is not implemented, the reset value is 0x00008000. If VFP and NEON are not implemented, the reset value is0x00000000.d. The reset value for bit[7] is UNK.e. The reset value depends on the VFP and NEON configuration. If VFP and NEON are implemented, the reset value is 0x000033FF. If VFPis implemented but NEON is not implemented, the reset value is 0x0000B3FF. If VFP and NEON are not implemented, the reset value is0x0000BFFF.4.2.3 c2 registersTable 4-4 shows the 32-bit wide CP15 system control registers when CRn is c2.Op1 CRm Op2 Name Reset Description0 c0 0 TTBR0 UNK Translation Table Base Register 0 and Register 1 on page 4-741 TTBR1 UNK Translation Table Base Register 0 and Register 1 on page 4-742 TTBCR 0x00000000 a Translation Table Base Control Register on page 4-744 c0 2 HTCR UNK Hyp Translation Control Register on page 4-75Table 4-4 c2 register summaryc1 2 VTCR UNK Virtualization Translation Control Register, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editiona. The reset value is 0x00000000 for the Secure copy of the register. The reset value for the EAE bit of the Non-secure copy of the register is0x0. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.4.2.4 c3 registersTable 4-5 shows the 32-bit wide CP15 system control registers when CRn is c3.Op1 CRm Op2 Name Reset DescriptionTable 4-5 c3 register summary0 c0 0 DACR UNK Domain Access Control Register, see the ARM ® Architecture Reference ManualARMv7-A and ARMv7-R edition4.2.5 c5 registersTable 4-6 shows the 32-bit wide CP15 system control registers when CRn is c5.Table 4-6 c5 register summaryOp1 CRm Op2 Name Reset Description0 c0 0 DFSR UNK Data Fault Status Register on page 4-751 IFSR UNK Instruction Fault Status Register on page 4-78c1 0 ADFSR UNK Auxiliary Data Fault Status Register on page 4-811 AIFSR UNK Auxiliary Instruction Fault Status Register on page 4-82ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-6ID062913Non-Confidential