ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt Controller8.2 GIC functional descriptionThis section provides a functional description of the Cortex-A15 MPCore GIC in:• GIC clock frequency.• GIC memory-map.• Interrupt sources on page 8-4.• Interrupt priority levels on page 8-5.• GIC configuration on page 8-6.The GIC is a single functional unit in the Cortex-A15 MPCore processor. The Cortex-A15MPCore GIC consists of a common Distributor block and several CPU interface blocks. Foreach processor in the system, there is:• A CPU interface.• A virtual interface control block.• A virtual CPU interface.8.2.1 GIC clock frequencyThe GIC can operate at any integer multiple that is slower than the main Cortex-A15 MPCoreprocessor clock, CLK, using the PERIPHCLKEN signal. For example, the CLK to internalGIC clock frequency ratio can be 2:1 or 3:1. The GIC does not support a 1:1 clock frequencyratio. See Clocks on page 2-8 for a description of PERIPHCLKEN.8.2.2 GIC memory-mapThe GIC registers are memory-mapped, with a physical base address specified byPERIPHBASE[39:15]. This input must be tied to a constant value. The PERIPHBASE valueis sampled during reset into the Configuration Base Address Register (CBAR) for eachprocessor in the MPCore device. See Configuration Base Address Register on page 4-106.Memory regions used for these registers must be marked as Device or Strongly-ordered in thetranslation tables.Access to these registers must be with the single load and store instructions. Load-multiple andload-double instructions result in a Data Abort exception to the requesting processor.Store-multiple and store-double instructions result in the assertion of nINTERRIRQ.Most of the registers can only be accessed with a word-size request. Some registers can also beaccessed with a byte-size request. Halfword and doubleword reads result in a Data Abortexception to the requesting processor. Halfword and doubleword writes result in the assertionof nINTERRIRQ.The Accelerator Coherency Port (ACP) cannot access any of the GIC registers. The registersmust be accessed through one of the processors. Any access from ACP to the GIC registers goesto external memory and no Data Abort exception is generated.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-3ID062913Non-Confidential