ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0ThumbEE_extn_instrsTrueNOP_instrsThumbCopy_instrsTabBranch_instrsSynchPrim_instrsSVC_instrsSIMD_instrsSaturate_instrsTable 4-44 shows the ID_ISAR3 bit assignments.Figure 4-16 ID_ISAR3 bit assignmentsTable 4-44 ID_ISAR3 bit assignmentsBits Name Function[31:28] ThumbEE_extn_instrs Indicates the supported Thumb Execution Environment (ThumbEE) extension instructions:0x1Processor supports ENTERX and LEAVEX instructions, and modifies the loadbehavior to include null checking.[27:24] TrueNOP_instrs Indicates support for True NOP instructions:0x1Processor supports true NOP instructions in both the ARM and Thumb instructionsets, and the capability for additional NOP-compatible hints.[23:20] ThumbCopy_instrs Indicates the supported Thumb non flag-setting MOV instructions:0x1Processor supports Thumb instruction set encoding T1 of the MOV (register)instruction, copying from a low register to a low register.[19:16] TabBranch_instrs Indicates the supported Table Branch instructions in the Thumb instruction set:0x1Processor supports TBB and TBH instructions.[15:12] SynchPrim_instrs This field is used with the SynchPrim_instrs_frac field of ID_ISAR4 to indicate the supportedSynchronization Primitive instructions.0x2Processor supports:• LDREX and STREX instructions.• CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.• LDREXD and STREXD instructions.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-45ID062913Non-Confidential