ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionThese pins are only present if you configure the Cortex-A15 MPCore processorto include them. If you configure the processor to include the CPUCLKOFFpins, there is one CPUCLKOFF input pin and a new top-level clock gateinstantiated for each processor. When CPUCLKOFF is asserted, the processorclock is stopped. This pin must be tied LOW or 1'b0 in normal functionaloperation, and can only be asserted under strict conditions. Having externalcontrol of the processor clock enable permits the SoC to assert CPUCLKOFFwhen the processor is already powered down, or when the processor is poweredup. However, CPUCLKOFF must be deasserted after power has beencompletely restored, at least 16 cycles before the deassertion of the processorreset, and at least 16 cycles before releasing the clamps on the processor outputs,to permit the powerup reset sequence to complete.NoteBecause configuring the Cortex-A15 MPCore processor with the CPUCLKOFFpins adds a new top-level clock gate for each processor, it might increase theclock skew between the processors.2.3.2 ResetsThe processor has the following reset inputs:nCPUPORESET[3:0]The nCPUPORESET signal initializes all the processor logic, includingthe NEON and VFP logic, Debug, PTM, breakpoint and watchpoint logicin the processor CLK domain. Each processor has one nCPUPORESETreset input.nCORERESET[3:0]The nCORERESET signal initializes the processor logic, including theNEON and VFP logic but excludes the Debug, PTM, breakpoint andwatchpoint logic. Each processor has one nCORERESET reset input.nCXRESET[3:0]The nCXRESET signal initializes the NEON and VFP logic. This resetcan be used to hold the NEON and VFP unit in a reset state so that thepower to the unit can be safely applied during power up. Each processorhas one nCXRESET reset input.nDBGRESET[3:0] The nDBGRESET signal initializes the Debug, PTM, breakpoint andwatchpoint logic in the processor CLK domain. Each processor has onenDBGRESET reset input.nPRESETDBGnL2RESETThe nPRESETDBG signal initializes the shared Debug APB, CTI, andCTM logic in the PCLKDBG domain.The nL2RESET signal initializes the shared L2 memory system, InterruptController, and Timer logic.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-11ID062913Non-Confidential